May 2007
rev 0.4
ASM3P623S00B/C/J/E/F/K
Timing-Safe™ Peak EMI reduction IC
General Features
•
•
•
•
Clock distribution with Timing-Safe™ Peak EMI
Reduction
Input frequency range: 20MHz - 50MHz
Zero input - output propagation delay
Low-skew outputs
•
•
•
•
Output-output skew less than 250pS
Device-device skew less than 700pS
ASM3P623S00B/C/J is the eight-pin version and accepts
one reference input and drives out one low-skew clock.
All parts have on-chip PLLs that lock to an input clock on
the CLKIN pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple ASM3P623S00E/F/K devices can accept the same
input clock and distribute it. In this case, the skew between
the outputs of the two devices is guaranteed to be less than
700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 250pS, and the output-to-output skew is
guaranteed to be less than 250pS.
Refer
“
Spread Spectrum Control and Input-Output Skew
Less than 200pS cycle-to-cycle jitter
Available in 16pin, 150mil SOIC, 4.4mm TSSOP
(ASM3P623S00/E/F/K), and in 8pin, 150 mil
SOIC, 4.4mm TSSOP Packages
(ASM3P623S00B/C/J)
•
•
•
•
3.3V operation
Industrial temperature range
Advanced CMOS technology
The First True Drop-in Solution
Functional Description
ASM3P623S00B/C/J/E/F/K is a versatile, 3.3V zero-delay
buffer designed to distribute high-speed Timing-Safe™
clocks with Peak EMI reduction. ASM3P623S00E/F/K
accepts one reference input and drives out eight low-skew
clocks.
It
is
available
in
a
16pin
V
DD
Table”
for
deviations
and
Input-Output
Skew for
ASM3P623S00B/C/J and the ASM3P623S00E/F/K devices
The ASM3P623S00B/C/J and the ASM3P623S00E/F/K are
available in two different packages, as shown in the
ordering information table.
package.
SSON
The
SS%
Block Diagram
Modulation
XIN/CLKIN
XOUT
Crystal
Oscillator
Reference
Divider
Feedback
Divider
Phase
Detector
Loop
Filter
VCO
PLL
Feedforward
Divider
CLKOUT
GND
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
May 2007
rev 0.4
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
wave is composed of fundamental frequency and
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of
EMI. Regulatory agencies test electronic equipment by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as
the frequency increases. The standard methods of
reducing EMI are to use shielding, filtering, multi-layer
ASM3P623S00B/C/J/E/F/K
PCBs etc. These methods are expensive. Spread
spectrum clocking reduces the peak energy by reducing
the Q factor of the clock. This is done by slowly
modulating
the
clock
frequency.
The
ASM3P623S00B/C/J/E/F/K uses the center modulation
spread spectrum technique in which the modulated
output frequency varies above and below the reference
frequency with a specified modulation rate. With center
modulation, the average frequency is the same as the
unmodulated frequency and there is no performance
degradation
Timing-Safe™ technology
Timing-Safe™ technology is the ability to modulate a
clock source with Spread Spectrum technology and
maintain synchronization with any associated data path.
Pin Configuration (8 Pin Devices)
CLKIN
NC
1
2
8
7
6
5
NC
V
DD
CLKOUT
SSON
ASM3P623S00B/C
SS%
3
GND
4
XIN/CLKIN
1
8
7
6
5
NC
V
DD
CLKOUT
SSON
XOUT
2
SS%
3
GND
4
ASM3P623S00J
Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 18
May 2007
rev 0.4
Pin Configuration (16 Pin Devices)
ASM3P623S00B/C/J/E/F/K
CLKIN
CLKOUT1
V
DD
SS%
GND
CLKOUT2
CLKOUT3
DLY CNTRL
1
2
3
4
5
6
7
8
16
15
14
CLKOUT
CLKOUT7
CLKOUT6
V
DD
GND
CLKOUT5
CLKOUT4
SSON
ASM3P623S00E/F
13
12
11
10
9
XIN/CLKIN
XOUT
CLKOUT1
VDD
SS%
GND
CLKOUT2
CLKOUT3
1
2
3
4
5
6
7
8
16
15
14
CLKOUT
CLKOUT7
CLKOUT6
V
DD
GND
CLKOUT5
CLKOUT4
SSON
ASM3P623S00K
13
12
11
10
9
Pin Description for ASM3P623S00B/C
Pin #
1
2
3
4
5
6
7
8
Pin Name
CLKIN
NC
SS%
3
GND
SSON
3
CLKOUT
1,2
VDD
NC
No Connect
Spread Spectrum Selection
Ground
Description
Input reference frequency, 5V-tolerant input
Spread Spectrum enable and disable option When SSON is HIGH, the spread
spectrum is enabled and when LOW, it turns off the spread spectrum.
Buffered clock output
3.3V supply
No Connect
Notes:
1. This output is driven and has an internal feedback for the PLL.
2. Weak pull-down on output. 3. Weak pull-up on these inputs. 4. Buffered clock output is Timing-Safe™
Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 18
May 2007
rev 0.4
Pin Description for ASM3P623S00J
Pin #
1
2
3
4
5
6
7
8
ASM3P623S00B/C/J/E/F/K
Pin Name
XIN/CLKIN
XOUT
SS%
3
GND
SSON
3
CLKOUT
1,2
VDD
NC
Description
Crystal connection or external reference frequency input. This pin has dual functions. It
can be connected either to an external crystal or an external reference clock.
Crystal connection. If using an external reference, this pin must be left unconnected.
Spread Spectrum Selection
Ground
Spread Spectrum enable and disable option When SSON is HIGH, the spread
spectrum is enabled and when LOW, it turns off the spread spectrum.
Buffered clock output
3.3V supply
No Connect
Notes:
1. This output is driven and has an internal feedback for the PLL.
2. Weak pull-down on output. 3. Weak pull-up on these inputs. 4. Buffered clock output is Timing-Safe™
Pin Description for ASM3P623S00E/F
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
CLKIN
CLKOUT1
1
VDD
SS%
2
GND
CLKOUT2
1
CLKOUT3
1
DLY CNTRL
SSON
3
CLKOUT4
1
CLKOUT5
1
GND
VDD
CLKOUT6
1
CLKOUT7
1
CLKOUT
1,3
Buffered clock output
3.3V supply
Spread Spectrum Selection
Ground
Buffered clock output
Buffered clock output
Description
Input reference frequency, 5V tolerant input
The pin is used to skew the outputs such that they align with the input. The skew can
is in the range of 100-200pS
Spread Spectrum enable and disable option. When SSON is HIGH, the spread
spectrum is enabled and when LOW, it turns off the spread spectrum.
Buffered clock output
Buffered clock output
Ground
3.3V supply
Buffered clock output
Buffered clock output
Buffered clock output
Notes:
1. Weak pull-down on all outputs. 2. Weak pull-up on these inputs.
3. This output is driven and has an internal feedback for the PLL.
4. Buffered clock outputs are Timing-Safe™
Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 18
May 2007
rev 0.4
Pin Description for ASM3P623S00K
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ASM3P623S00B/C/J/E/F/K
Pin Name
XIN/CLKIN
XOUT
CLKOUT1
1
VDD
SS%
2
GND
CLKOUT2
1
CLKOUT3
1
SSON
2
CLKOUT4
1
CLKOUT5
1
GND
VDD
CLKOUT6
1
CLKOUT7
1
CLKOUT
1,3
Description
Crystal connection or external reference frequency input. This pin has dual functions. It
can be connected either to an external crystal or an external reference clock.
Crystal connection. If using an external reference, this pin must be left unconnected.
Buffered clock output
3.3V supply
Spread Spectrum Selection
Ground
Buffered clock output
Buffered clock output
Spread Spectrum enable and disable option. When SSON is HIGH, the spread
spectrum is enabled and when LOW, it turns off the spread spectrum.
Buffered clock output
Buffered clock output
Ground
3.3V supply
Buffered clock output
Buffered clock output
Buffered clock output
Notes: 1. Weak pull-down on all outputs. 2. Weak pull-up on these inputs.
3. This output is driven and has an internal feedback for the PLL.
4. Buffered clock outputs are Timing-Safe™
Spread Spectrum Control and Input-Output Skew Table
(Note: The values given in the table are for an input frequency of 32MHz)
Device
ASM3P623S00B
SS%
0
1
0
1
0
1
0
1
0
1
0
1
Deviation
±0.25 %
±0.5 %
±0.125 %
±0.25 %
±0.125 %
±0.25 %
±0.25 %
±0.5 %
±0.125 %
±0.25 %
±0.125 %
±0.25 %
Input-Output Skew(±T
SKEW
)
0.125
0.25
0.125
0.25
0.125
0.25
0.125
0.25
0.125
0.25
0.125
0.25
ASM3P623S00C
ASM3P623S00J
ASM3P623S00E
ASM3P623S00F
ASM3P623S00K
Note: T
SKEW
is measured in units of the Clock Period
Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
5 of 18
FPGA/CPLD
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