- Up to 240 Individually-Vectored Interrupt Sources
Supported
- 8 Levels of Priority, Individually Assignable By Vector
- Chip-Level Interrupt Aggregator supported, to
expand number of interrupt sources or reduce
number of vectors
•
•
- System Tick Timer
- Complete ARM-Standard Debug Support
- JTAG-Based DAP Port, Comprised of SWJ-DP and
AHB-AP Debugger Access Functions
- Full DWT Hardware Functionality: 4 Data
Watchpoints and Execution Monitoring
- Full FPB Hardware Breakpoint Functionality: 6
Execution Breakpoints and 2 Literal (Data)
Breakpoints
- Comprehensive ARM-Standard Trace Sup-
port
- Full DWT Hardware Trace Functionality for
Watchpoint and Performance Monitoring
- Full ITM Hardware Trace Functionality for
Instrumented Firmware Support and Profiling
- Full TPIU Functionality for Trace Output
Communication
•
•
- Fully Operational on Standby Power
- DMA-driven I
2
C Network Layer Hardware
- I
2
C Datalink Compatibility Mode
- Multi-Master Capable
- Supports Clock Stretching
- Programmable Bus Speed up to 1MHz
- Hardware Bus Access “Fairness” Interface
- SMBus Time-outs Interface
- All Ports Assignable to Any Controller
- All ports 1.8V-capable
General Purpose Serial Peripheral Interface Con-
troller
- One 4-pin Full Duplex Serial Communication
Interface
- Flexible Clock Rates
- SPI Burst Capable
One Quad Serial Peripheral Interface (SPI) Con-
troller
- Master Only SPI Controller
- Mappable to two ports (only 1 port active at a
time)
- Dual and Quad I/O Support
- Flexible Clock Rates
- SPI Burst Capable
- SPI Controller Operates with Internal DMA
Controller with CRC Generation
13 x 8 Interrupt Capable Multiplexed Keyboard
Scan Matrix
- Optional Push-Pull Drive for Fast Signal
Switching
Two Breathing/Blinking LED Interfaces
- Supports three modes of operation:
- Blinking Mode with Programmable Blink Rates
- Breathing LED Output
- 8-bit PWM
- MPU Feature
- 1µS Delay Register
• Internal Memory
- 64k Boot ROM
- Two blocks of SRAM, totaling 480KB
- Each block can be used for either program or data
- Breathing LED Supports Piecewise-linear
Brightness Curves, Symmetric or Asymmetric
- Supports Low Power Operation in Blinking
and Breathing Modes
- Operates on Standby Power
- Operates in Chip's System Deepest Sleep State on
32kHz standby clock
- Operational in EC Sleep State
- 128 Bytes Battery Powered SRAM
• Battery Backed Resources
- Power-Fail Status Register
- 32 KHz Clock Generator
- Week Alarm Timer Interface
- Real Time Clock
- VBAT-Powered Control Interface
- Two Wake-up Input Signals
- Optional Latching of Wake-up Inputs
- VBAT-Backed 128 Byte Memory
• Four I
2
C Host Controllers
- Allows Master or Dual Slave Operation
- Pin buffers capable of sinking up to 12 mA
• Two Resistor/Capacitor Identification Detection
(RC_ID) ports
- Single Pin Interface to External Inexpensive
RC Circuit
- Replacement for Multiple GPIO’s
- Provides 8 Quantized States on One Pin
• General Purpose I/O Pins
- Up to 65 GPIOs
2016-2017 Microchip Technology Inc.
DS00002207C-page 1
CEC1702
Glitch protection on most GPIO pins
1 Battery-powered General Purpose Outputs
All GPIOs can be powered by 1.8V
Programmable Drive Strength and Slew Rate
on all GPIOs
• Programmable 16-bit Counter/Timer Interface
- Four 16-bit Auto-reloading Counter/Timer
Instances
- Four Operating Modes per Instance: Timer,
One-shot, Event and Measurement
- 3 External Inputs
- 2 External Outputs
-
-
-
-
- Spin Up Routine
- Ramp Rate Control
- RPM-based Fan Speed Control Algorithm
• Hibernation Timer Interface
- Two 32.768 KHz Driven 16-bit Timers
- Programmable Wake-up from 0.5ms to 128 Minutes
- One 32.768 KHz Driven 32-bit RTOS Timer
- Programmable Wake-up from 30μS to 35 Hours
- Auto Reload Option
• System Watch Dog Timer (WDT)
• Input Capture Timer
- 32-bit Free-running timer
- Four 32-bit Capture Registers
- One Compare Timer with Optional Toggling
Output
- Capture Interrupts with Programmable Edge
Detection
- Compare Timer and Counter Overflow Inter-
rupts
• Week Timer
- Power-up Event Output
- Week Alarm Interrupt with 1 Second to 8.5 Year
Time-out
- Sub-Week Alarm Interrupt with 0.50 Seconds -
72.67 hours time-out
- 1 Second and Sub-second Interrupts
• Real Time Clock (RTC)
- VBAT Powered
- 32KHz Crystal Oscillator
- Time-of-Day and Calendar Registers
- Programmable Alarms
- Supports Leap Year and Daylight Savings Time
• Pulse-Width Modulator Support
- Seven Programmable PWM Outputs
- Multiple Clock Rates
- 16-Bit ‘On’ and 16-Bit ‘Off’ Counters
• ADC Interface
- 10-bit Conversion in 1s
- 5 Channels
- Integral Non-Linearity of ±1.5 LSB; Differential
Non-Linearity of ±1.0 LSB
• Two Standard 16C550 UARTs
- Both UARTs with 4-pin Interface
- Programmable Input/output Pin Polarity Inver-
sion
- Programmable Main Power or Standby Power
Functionality
• Trace FIFO Debug Port (TFDP)
• Integrated Standby Power Reset Generator
- Reset Input Pin
• Clock Generator
- 32.768KHz Clock Source
- Low power 32KHz crystal oscillator
- Optional use of a crystal-free silicon oscillator with ±2%
Accuracy
- Optional use of 32.768 KHz input Clock
- Operational on Suspend Power
•
•
•
- Optional Inverted Output
• FAN Support
- Two Fan Tachometer Inputs
- Two RPM-Based Fan Speed Controllers
-
-
-
-
Each includes one Tach input and one PWM output
3% accurate from 500 RPM to 16k RPM
Automatic Tachometer feedback
Aging Fan or Invalid Drive Detection
•
•
- Programmable Clock Power Management Con-
trol and Distribution
- 48 MHz PLL
Multi-purpose AES Cryptographic Engine
- Hardware support for ECB, CTR, CBC and
OFB AES modes
- Support for 128-bit, 192-bit and 256-bit key
length
- DMA interface to SRAM, shared with Hash
engine
Cryptographic Hash Engine
- Support for SHA-1, SHA-256, SHA-512
- DMA interface to SRAM, shared with AES
engine
Public Key Cryptographic Engine
- Hardware support for RSA and Elliptic Curve
public key algorithms
- RSA keys length from 1024 to 4096 bits
- ECC Prime Field and Binary Field keys up to
640 bits
- Microcoded support for standard public key
algorithms
Cryptographic Features
- True Random Number Generator
- 1K bit FIFO
- Monotonic Counter
Package
- 84 Pin WFBGA RoHS Compliant package
DS00002207C-page 2
2016-2017 Microchip Technology Inc.
CEC1702
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Micro-
chip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined
and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at
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We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-
rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site;
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• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
using.
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Register on our web site at
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to receive the most current information on all of our products.
2016-2017 Microchip Technology Inc.
DS00002207C-page 3
CEC1702
Table of Contents
1.0 General Description ........................................................................................................................................................................ 5
5.0 Power, Clocks, and Resets ........................................................................................................................................................... 69
6.0 ARM M4F Based Embedded Controller ........................................................................................................................................ 83
7.0 RAM and ROM .............................................................................................................................................................................. 93
18.0 Real Time Clock ........................................................................................................................................................................ 200
22.0 Analog to Digital Converter ....................................................................................................................................................... 236
28.0 General Purpose Serial Peripheral Interface ............................................................................................................................ 296
35.0 Security Features ...................................................................................................................................................................... 363
36.0 Test Mechanisms ...................................................................................................................................................................... 367
Appendix A: Data Sheet Revision History ......................................................................................................................................... 408
DS00002207C-page 4
2016-2017 Microchip Technology Inc.
CEC1702
1.0
GENERAL DESCRIPTION
The CEC1702 is a family of embedded controller designs with strong cryptographic support, customized for Internet of
Things (IOT) platforms. The family is a highly-configurable, mixed signal, advanced I/O controller architecture. The
device incorporates a 32-bit ARM Cortex M4F Microcontroller core with a closely-coupled SRAM for code and data. A
secure boot-loader is used to download the custom firmware image from the system’s shared SPI Flash device, thereby
allowing system designers to customize the device’s behavior.
The CEC1702 is directly powered by a minimum of two separate suspend supply planes (VBAT and VTR). There are
three voltage supply regions for all GPIO pins. Two regions may be either 3.3V or 1.8V.
The CEC1702 family of devices offer a software development system interface that includes a Trace FIFO Debug port
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