NVT224
dbCOOLt Remote Thermal
Monitor and Fan Controller
The NVT224 dbCOOL controller is a thermal monitor and multiple
PWM fan controller for noise−sensitive or power−sensitive
applications requiring active system cooling. The NVT224 can drive a
fan using either a low or high frequency drive signal, monitor the
temperature of up to two remote sensor diodes plus its own internal
temperature, and measure and control the speed of up to four fans so
that they operate at the lowest possible speed for minimum acoustic
noise.
The automatic fan speed control loop optimizes fan speed for a
given temperature. The effectiveness of the system’s thermal solution
can be monitored using the THERM input. The NVT224 also provides
critical thermal protection to the system using the bidirectional
THERM pin as an output to prevent system or component overheating.
The NVT224 has been through Automotive Qualification according
to AEC−Q100 Grade 1 standards.
Features
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QSOP−16
CASE 492
MARKING DIAGRAMS
TOP MARKING
BOTTOM MARKING
NVT
224
GYYWW
ZZZZ
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controls and Monitors Up to 4 Fans
High and Low Frequency Fan Drive Signal
1 On−Chip and 2 Remote Temperature Sensors
Extended Temperature Measurement Range, Up to 191°C
Automatic Fan Speed Control Mode Controls System Cooling Based
on Measured Temperature
Enhanced Acoustic Mode Dramatically Reduces User Perception of
Changing Fan Speeds
Thermal Protection Feature via THERM Output
Monitors Performance Impact of Intel Pentium
R
4 Processor
Thermal Control Circuit via THERM Input
3−Wire and 4−Wire Fan Speed Measurement
Limit Comparison of All Monitored Values
Meets SMBus 2.0 Electrical Specifications
(Fully SMBus 1.1 Compliant)
Automotive Qualification According to AEC−Q100 Grade 1
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
NVT224 = Specific Device Code
G
= Pb−Free Package
YY
= Year
WW
= Work Week
ZZZZ = Assembly Lot Code
PIN ASSIGNMENT
SCL
1
GND
2
V
CC 3
TACH3
4
PWM2/
5
SMBALERT
TACH1
6
TACH2
7
PWM3
8
16
SDA
15
PWM1/XTO
14
V
CCP
NVT224
TOP VIEW
13
D1+
12
D1–
11
D2+
10
D2–
9
TACH4/GPIO/THERM
SMBALERT
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 57 of this data sheet.
©
Semiconductor Components Industries, LLC, 2012
1
October, 2016 − Rev. 2
Publication Order Number:
NVT224/D
NVT224
SCL SDA SMBALERT
NVT224
SERIAL BUS
INTERFACE
PWM1
PWM2
PWM3
PWM
REGISTERS
AND
CONTROLLERS
(HF AND LF)
ACOUSTIC
ENHANCEMENT
CONTROL
AUTOMATIC
FAN SPEED
CONTROL
ADDRESS
POINTER
REGISTER
TACH1
TACH2
TACH3
TACH4
FAN
SPEED
COUNTER
PERFORMANCE
MONITORING
PWM
CONFIGURATION
REGISTERS
INTERRUPT
MASKING
THERM
V
CC
D1+
D1–
D2+
D2–
V
CCP
BAND GAP
TEMPERATURE
SENSOR
V
CC
TO NVT224
THERMAL
PROTECTION
INTERRUPT
STATUS
REGISTERS
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
10−BIT
ADC
LIMIT
COMPARATORS
BAND GAP
REFERENCE
VALUE AND
LIMIT
REGISTERS
GND
Figure 1. Functional Block Diagram
ABSOLUTE MAXIMUM RATINGS
Parameter
Positive Supply Voltage (V
CC
)
Voltage on Any Input or Output Pin
Input Current at Any Pin
Package Input Current
Maximum Junction Temperature (T
JMAX
)
Storage Temperature Range
Lead Temperature, Soldering
IR Reflow Peak Temperature
Lead Temperature (Soldering, 10 sec)
ESD Rating
Human Body Model
Machine Model
Charged Device Model
Rating
3.6
−0.3 to +3.6
±5
±20
150
−65 to +150
260
300
V
1000
100
1000
Unit
V
V
mA
mA
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
THERMAL CHARACTERISTICS
Package Type
16−lead QSOP
q
JA
150
q
JC
39
Unit
°C/W
1.
q
JA
is specified for the worst−case conditions, that is, a device soldered in a circuit board for surface−mount packages.
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2
NVT224
PIN ASSIGNMENT
Pin No.
1
2
3
4
5
Mnemonic
SCL
GND
VCC
B
Description
Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pullup.
Ground Pin.
Power Supply. VCC is also monitored through this pin.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.
PWM2: Digital Output (Open Drain). Requires 10 kW typical pullup. Pulse−width modulated output to
control Fan 2 speed. Can be configured as a high or low frequency drive.
SMBALERT: Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt
output to signal out−of−limit conditions.
Digital Input (Open Drain). Fan tachometer input to measure the speed of Fan 1.
Digital Input (Open Drain). Fan tachometer input to measure the speed of Fan 2.
Digital I/O (Open Drain). Pulse−width modulated output to control the speed of Fan 3 and Fan 4.
Requires 10 kW typical pullup. Can be configured as a high or low frequency drive.
TACH4: Digital Input (Open Drain). Fan tachometer input to measure the speed of Fan 4.
THERM: Digital I/O (Open Drain). Alternatively, this pin can be reconfigured as a bidirectional THERM
pin that can be used to time and monitor assertions on the THERM input. For example, the pin can be
connected to the PROCHOT output of an Intel Pentium 4 processor or to the output of a trip point
temperature sensor. This pin can be used as an output to signal overtemperature conditions.
GPIO: General−Purpose Open Drain Digital I/O.
SMBALERT: Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt
output to signal out−of−limit conditions.
Cathode Connection to Second Thermal Diode.
Anode Connection to Second Thermal Diode.
Cathode Connection to First Thermal Diode.
Anode Connection to First Thermal Diode.
Analog Input. Monitors processor core voltage (0 V to 3.0 V).
Digital Output (Open Drain). Pulse−width modulated output to control Fan 1 speed. Requires 10 kW
typical pullup.
Also functions as the output from the XNOR tree in XNOR test mode.
Digital I/O (Open Drain). SMBus bidirectional serial data. Requires 10 kW typical pullup.
TACH3
PWM2
SMBALERT
6
7
8
9
TACH1
TACH2
PWM3
TACH4
THERM
GPIO
SMBALERT
10
11
12
13
14
15
D2−
D2+
D1−
D1+
VCCP
B
PWM1
XTO
16
SDA
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NVT224
ELECTRICAL CHARACTERISTICS
T
A
= T
MIN
to T
MAX
, V
CC
= V
MIN
to V
MAX
, unless otherwise noted. (Note 1)
Parameter
Power Supply
Supply Voltage
Supply Current, I
CC
Temperature−to−Digital Converter
Local Sensor Accuracy
Resolution
Remote Diode Sensor Accuracy
Resolution
Remote Sensor Source Current
High level
Low level
0°C
≤
T
A
≤
85°C
−40°C
≤
T
A
≤
+125°C
0°C
≤
T
A
≤
85°C
−40°C
≤
T
A
≤
+125°C
±0.5
0.25
±0.5
0.25
180
11
±2
8 bits
±0.1
Averaging enabled
Averaging enabled
Averaging enabled
Averaging enabled
Averaging disabled
For V
CCP
channel
0°C
≤
T
A
≤
70°C
−40°C
≤
T
A
≤
+120°C
Fan count = 0xBFFF
Fan count = 0x3FFF
Fan count = 0x0438
Fan count = 0x021C
109
329
5000
10,000
70
11
12
38
145
19
120
±6
±10
65,535
RPM
±1
mA
1.5
±2.5
°C
±1.5
±2.5
°C
Interface inactive, ADC active
3.0
3.3
1.5
3.6
3.0
V
mA
Conditions
Min
Typ
Max
Unit
ANALOG−TO−DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error (TUE)
Differential Non−linearity (DNL)
Power Supply Sensitivity
Conversion Time (Voltage Input)
Conversion Time (Local Temperature)
Conversion Time (Remote Temperature)
Total Monitoring Cycle Time
Input Resistance
FAN RPM−TO−DIGITAL CONVERTER
Accuracy
Full−Scale Count
Nominal Input RPM
%
%
LSB
%/V
ms
ms
ms
ms
kW
OPEN−DRAIN DIGITAL OUTPUTS (PWM1 TO PWM3, XTO)
Current Sink, I
OL
Output Low Voltage, V
OL
High Level Output Current, I
OH
Output Low Voltage, V
OL
High Level Output Current, I
OH
SMBus DIGITAL INPUTS (SCL, SDA)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, V
IH
Maximum input voltage
Input Low Voltage, V
IL
Minimum input voltage
Hysteresis
−0.3
0.5
V p−p
2.0
3.6
0.8
V
V
500
2.0
0.4
V
V
mV
I
OUT
= −8.0 mA
V
OUT
= V
CC
I
OUT
= −4.0 mA
V
OUT
= V
CC
0.1
0.1
8.0
0.4
20
mA
V
mA
V
mA
OPEN−DRAIN SERIAL DATA BUS OUTPUT (SDA)
0.4
1.0
1. All voltages are measured with respect to GND, unless otherwise specified. Typicals are at T
A
= 25°C and represent the most likely
parametric norm. Logic inputs accept input high voltages of up to V
MAX
, even when the device is operating down to V
MIN
. Timing
specifications are tested at logic levels of V
IL
= 0.8 V for a falling edge and V
IH
= 2.0 V for a rising edge.
2. SMBus timing specifications are guaranteed by design and are not production tested.
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NVT224
ELECTRICAL CHARACTERISTICS
T
A
= T
MIN
to T
MAX
, V
CC
= V
MIN
to V
MAX
, unless otherwise noted. (Note 1)
Parameter
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, V
IH
Input Low Voltage, V
IL
DIGITAL INPUT CURRENT
Input High Current, I
IH
Input Low Current, I
IL
Input Capacitance, C
IN
SERIAL BUS TIMING
Clock Frequency, f
SCLK
Glitch Immunity, t
SW
Bus Free Time, t
BUF
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
R
SCL, SDA Fall Time, t
F
Data Setup Time, t
SU: DAT
Detect Clock Low Timeout, t
TIMEOUT
Can be optionally disabled
250
15
35
4.7
4.7
4.0
50
1000
300
See Note 2 and Figure 2
10
400
50
kHz
ns
ms
ms
ms
ns
ns
ns
ms
V
IN
= V
CC
V
IN
= 0 V
±1
±1
5
mA
mA
pF
0.75 x V
CC
0.8
V
V
Conditions
Min
Typ
Max
Unit
1. All voltages are measured with respect to GND, unless otherwise specified. Typicals are at T
A
= 25°C and represent the most likely
parametric norm. Logic inputs accept input high voltages of up to V
MAX
, even when the device is operating down to V
MIN
. Timing
specifications are tested at logic levels of V
IL
= 0.8 V for a falling edge and V
IH
= 2.0 V for a rising edge.
2. SMBus timing specifications are guaranteed by design and are not production tested.
t
LOW
SCL
t
R
t
F
t
HD: STA
t
HIGH
t
HD: STA
t
HD: DAT
t
SU: DAT
t
SU: STA
t
SU: STO
SDA
t
BUF
P
S
S
P
Figure 2. Serial Bus Timing Diagram
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