LCP154DJF
Programmable transient voltage suppressor for SLIC protection
Datasheet
-
production data
Description
This device has been especially designed to
protect new high voltage, as well as classical
SLICs, against transient overvoltages.
Positive overvoltages are clamped by 2 diodes.
Negative surges are suppressed by 2 thyristors,
their breakdown voltage being referenced to -V
BAT
through the gate.
LCP154DJF is specified to comply with
ITU-T K20/21/45 and GR1089-Core when
associated with Cooper Bussmann Telecom
Circuit Protector fuse TCP 1.25 A.
Features
•
Programmable transient suppressor
•
Wide negative firing voltage range: V
Gn
= -
175 V max.
•
Low dynamic switching voltages: V
FP
and V
DGL
•
Low gate triggering current: I
GT
= 5 mA max.
•
Peak pulse current:
– I
PP
= 100 A (10/1000 µs)
– I
PP
= 150 A (5/310 µs)
– I
PP
= 500 A (2/10 µs)
•
Holding current: I
H
= 150 mA min.
LCP154DJF is packaged in a PowerFLAT™ 5x6
to meet IEC/UL 60950 clearance requirements.
Figure 1. Functional diagram
Benefits
•
Trisil™ is not subject to ageing and provides a
fail safe mode in short circuit for a better level
of protection.
•
Trisils are used to ensure equipment meets
various standards such as UL60950,
IEC 60950 / CSA C22.2, UL1459, TIA-968-A
(formerly FCC part 68)
•
Trisils have UL94 V0 approved resin (Trisils
are UL497B approved [file: E136224]).
TM:
Trisil is a trademark of STMicroelectronics
September 2015
This is information on a product in full production.
DocID028213 Rev 1
1/13
www.st.com
Characteristics
LCP154DJF
1
Characteristics
Table 1. Standards compliance
Peak
surge
voltage
(V)
GR-1089 Core First level
GR-1089 Core
Second level
GR-1089 Core
Intra-building
ITU-T-K20/K21
ITU-T-K20 (IEC 61000-4-2)
IEC 61000-4-5
TIA-968-A,
lightning surge type A
TIA-968-A,
lightning surge type B
2500
1000
5000
1500
6000
1500
8000
15000
4000
4000
1500
800
1000
2/10 µs
10/1000 µs
2/10 µs
2/10 µs
10/700 µs
1/60 ns
10/700 µs
1.2/50 µs
10/160 µs
10/560 µs
9/720 µs
Voltage
waveform
Required
peak
current
(A)
500
100
500
100
150
37.5
2/10 µs
10/1000 µs
2/10 µs
2/10 µs
5/310 µs
Current
waveform
Minimum serial
resistor to meet
standard (
Ω
)
0
0
0
0
0
0
0
0
0
0
0
0
0
Standard
ESD contact discharge
ESD air discharge
100
100
200
100
25
5/310 µs
8/20 µs
10/160 µs
10/560 µs
5/320 µs
2/13
DocID028213 Rev 1
LCP154DJF
Table 2. Absolute ratings (T
amb
= 25 °C)
Symbol
Parameter
10/1000 µs
8/20 µs
10/560 µs
5/310 µs
10/160 µs
1/20 µs
2/10 µs
Characteristics
Value
100
400
140
150
200
400
500
35
18
12
10
4
3
-175
-55 to +150
-55 to +150
260
Unit
I
PP
Peak pulse current
(1)
A
I
TSM
t = 10 ms
t = 0.2 s
Non repetitive surge peak on-state current t = 1 s
t=2s
(50 Hz sinusoidal)
(1)
t = 15 min
t = 30 min
Negative battery voltage
Storage temperature range
Operating junction temperature range
Maximum lead temperature for soldering during 10 s.
A
V
GN
T
stg
T
j
T
L
V
°C
°C
1. The rated current values may be applied either to the RING to GND or to the Tip to GND terminal pairs.
Additionally, both terminal pairs may have their rated current values applied simultaneously (in this case
the GND terminal current will be twice the rated current value of an individual terminal pair).
Figure 2. Electrical characteristics (definitions)
I
Symbol
I
GT
V
FP
V
GT
V
F
I
RG
I
H
V
RG
V
DGL
I
PP
I
R
V
F
C
=
=
=
=
=
=
=
=
=
=
=
=
Parameter
Gate triggering current
Peak forward voltage LINE / GND
Gate triggering voltage
Forward drop voltage LINE /GND
Reverse leakage current GATE / LINE
Holding current
Reverse voltage GATE / LINE
Dynamic switching voltage GATE / LINE
Peak pulse current
Breakdown current
Forward drop voltage LINE / GND
Capacitance LINE /GND
V
R
V
F
I
R
I
H
V
I
PP
DocID028213 Rev 1
3/13
13
Characteristics
Figure 3. Pulse waveform
LCP154DJF
Table 3. Parameters (T
amb
= 25 °C unless otherwise specified)
Symbol
I
GT
I
H
V
GT(1)
I
RG
V
DGL(1)
V
F
V
FP(I)
I
R
C
C
G
V
LINE
= -48 V
V
Gn
= -48 V
at I
GT
V
RG
= -175 V
V
RG
= -175 V
V
Gn
= -48 V
(1)
I
F
= 5 A
10/700 µs
2/10 µs
V
Gn / LINE
= -1 V
V
Gn / LINE
= -1 V
V
LINE
= -175 V
V
LINE
= -175 V
10/700 µs
2/10 µs
T
j
= 25 °C
T
j
= 85 °C
I
PP
= 150 A
I
PP
= 200 A
t = 500 µs
I
pp
= 150 A
I
pp
= 200 A
T
j
= 25 °C
T
j
= 85 °C
35
100
100
220
Test conditions
Min
0.1
150
2.5
5
50
12
20
3
7
10
5
50
Typ
Max
5
Unit
mA
mA
V
µA
V
V
V
µA
pF
nF
V
LINE
= -50 V, V
RMS
= 1 V, f = 1 MHz
V
LINE
= -2 V, V
RMS
= 1 V, f = 1 MHz
Gate decoupling capacitance
1. The oscillations with a time duration lower than 50 ns are not taken into account.
4/13
DocID028213 Rev 1
LCP154DJF
Technical information
2
Technical information
Figure 4. Example of PCB layout based on LCP154DJF protection
To
line side
>2 mm
To
SLIC
side
GND
100 nF
GND
Figure 4
shows the classical PCB layout used to optimize line protection. The 2 mm
distance is used to comply with IEC/UL 60950 clearance requirements.
The capacitor C is used to speed up the crowbar structure firing during the fast surge edges.
This allows minimization of the dynamic breakover voltage at the SLIC Tip and Ring inputs
during fast strikes. Note that this capacitor is generally present around the SLIC - Vbat pin.
So to be efficient it has to be as close as possible from the LCP Gate pin and from the
reference ground track (or plan).
The schematics of
Figure 5
give the topology used to protect all SLICs according to ITU-T
K20/21/45 and GR1089-Core.
Figure 5. Protection of high voltage SLIC
DocID028213 Rev 1
5/13
13
能源基础设施
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
