SO
T4
PUSB2X4D
ESD protection for high-speed interfaces
Rev. 1 — 5 November 2013
Product data sheet
1. Product profile
1.1 General description
The device is designed to protect high-speed interfaces such as USB 2.0 ports against
ElectroStatic Discharge (ESD).
The device includes four high-level ESD protection diode structures for high-speed signal
lines. It is encapsulated in a small SOT457 (SC-74) Surface-Mounted Device (SMD)
plastic package.
All signal lines are protected by a special diode configuration offering ultra low line
capacitance of 0.85 pF maximum. This configuration provides protection to downstream
components from ESD voltages up to
12
kV contact according to IEC 61000-4-2, level 4.
57
1.2 Features and benefits
System ESD protection for USB 2.0
All signal lines with integrated rail-to-rail clamping diodes for downstream
ESD protection of
12
kV according to IEC 61000-4-2, level 4
Line capacitance of 0.85 pF maximum for each channel
1.3 Applications
The device is designed for receiver and transmitter port protection in:
Portable devices
TVs, monitors
DVD recorders and players
Notebooks, mother boards, graphic cards and ports
Set-top boxes and game consoles
NXP Semiconductors
PUSB2X4D
ESD protection for high-speed interfaces
2. Pinning information
Table 1.
Pin
1
2
3
4
5
6
Pinning
Description
ESD protection for I/O signals
ground
ESD protection for I/O signals
ESD protection for I/O signals
n.c.
ESD protection for I/O signals
2
018aaa176
Simplified outline
6
5
4
Graphic symbol
1
3
4
6
1
2
3
3. Ordering information
Table 2.
Ordering information
Package
Name
PUSB2X4D
SC-74
Description
plastic surface-mounted package; 6 leads
Version
SOT457
Type number
4. Marking
Table 3.
Marking codes
Marking code
DE
Type number
PUSB2X4D
5. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
I
V
ESD
Parameter
input voltage
electrostatic discharge
voltage
pins 1, 3, 4 and 6 to ground;
IEC 61000-4-2, level 4
contact discharge
air discharge
T
amb
T
stg
ambient temperature
storage temperature
12
15
40
55
+12
+15
+85
+125
kV
kV
C
C
Conditions
Min
0.5
Max
+5.5
Unit
V
PUSB2X4D
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 November 2013
2 of 11
NXP Semiconductors
PUSB2X4D
ESD protection for high-speed interfaces
6. Characteristics
Table 5.
Characteristics
T
amb
= 25
C unless otherwise specified.
Symbol
V
BR
I
RM
V
F
C
line
Parameter
breakdown voltage
reverse leakage current
forward voltage
line capacitance
Conditions
I
I
= 1 mA
per channel; V
I
= 5 V
I
I
= 1 mA
f = 1 MHz
V
I
= 0 V
V
I
= 2.5 V
C
line
r
dyn
line capacitance
difference
dynamic resistance
f = 1 MHz; V
I
= 2.5 V
surge
positive transient
negative transient
TLP
positive transient
negative transient
V
CL
clamping voltage
positive transient
I
PP
= 4.8 A
negative transient
I
PP
=
5.2
A
[1]
[2]
[3]
This parameter is guaranteed by design.
According to IEC 61000-4-5 (8/20
s
current waveform).
100 ns Transmission Line Pulse (TLP); 50
;
pulser at 80 ns.
[2]
[3]
[1]
[1]
Min
6
-
-
-
-
-
Typ
-
-
0.7
0.7
0.6
-
Max
9
1
-
0.85
0.75
0.1
Unit
V
A
V
pF
pF
pF
[2]
-
-
-
-
-
-
0.41
0.34
0.48
0.34
4.3
2.7
-
-
-
-
-
-
V
V
PUSB2X4D
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 November 2013
3 of 11
NXP Semiconductors
PUSB2X4D
ESD protection for high-speed interfaces
0
S
21
(dB)
-2
aaa-009805
0
S
21
(dB)
-30
aaa-009806
-4
-6
-60
-8
-10
1
10
10
2
10
3
f (MHz)
10
4
-90
10
10
2
10
3
f (MHz)
10
4
Fig 1.
Insertion loss; typical values
1.2
a
Fig 2.
Crosstalk; typical values
aaa-009807
0.8
0.4
0
0
1
2
3
4
V
I
(A)
5
C
line
a
=
---------------------------------
C
line
V
=
0
V
I
Fig 3.
Relative capacitance as a function of input voltage; typical values
PUSB2X4D
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 November 2013
4 of 11
NXP Semiconductors
PUSB2X4D
ESD protection for high-speed interfaces
6
I
PP
(A)
4
aaa-009808
0
I
PP
(A)
-2
aaa-009809
2
-4
0
0
1
2
3
4
V
CL
(V)
5
-6
-3
-2
-1
V
CL
(V)
0
IEC 61000-4-5; t
p
= 8/20
s;
positive pulse
IEC 61000-4-5; t
p
= 8/20
s;
negative pulse
Fig 4.
Dynamic resistance with positive clamping;
typical values
15
aaa-009810
Fig 5.
Dynamic resistance with negative clamping,
typical values
0
aaa-009811
I
(A)
12
I
(A)
-3
9
-6
6
-9
3
-12
0
0
4
8
V
CL
(V)
12
-15
-8
-6
-4
-2
V
CL
(V)
0
t
p
= 100 ns; Transmission Line Pulse (TLP)
t
p
= 100 ns; Transmission Line Pulse (TLP)
Fig 6.
Dynamic resistance with positive clamping,
typical values
Fig 7.
Dynamic resistance with negative clamping;
typical values
The device uses an advanced clamping structure, which shows a negative dynamic
resistance. This snap-back behavior strongly reduces the clamping voltage to the system
behind the ESD protection during an ESD event. Do not connect unlimited DC current
sources to the data lines to avoid keeping the ESD protection device in snap-back state
after exceeding breakdown voltage (due to an ESD pulse for instance).
PUSB2X4D
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 November 2013
5 of 11
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