CM1216
6 and 8-Channel Low
Capacitance ESD Arrays
Product Description
The CM1216 family of diode arrays provide sESD protection for
electronic components or sub−systems requiring minimal capacitive
loading. These devices are ideal for protecting systems with high data
and clock rates or for circuits requiring low capacitive loading. Each
ESD channel consists of a pair of diodes in series which steer the
positive or negative ESD current pulse to either the positive (V
P
) or
negative (V
N
) supply rail. The CM1216 protects against ESD pulses
up to
±
15 kV per the IEC 61000−4−2 standard.
This device is particularly well−suited for protecting systems using
high−speed ports such as USB2.0, IEEE1394 (Firewire
®
, iLinkt),
Serial ATA, DVI, HDMI and corresponding ports in removable
storage, digital camcorders, DVD−RW drives and other applications
where extremely low loading capacitance with ESD protection are
required in a small package footprint.
Features
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SOIC−8
SM SUFFIX
CASE 751AC
MSOP−8
MR SUFFIX
CASE 846AD
MSOP−10
MR SUFFIX
CASE 846AE
BLOCK DIAGRAM
CH6
V
P
CH5 CH4
•
Six and Eight Channels of ESD Protection
•
Provides
±15
kV ESD Protection on Each Channel per the
•
•
•
•
•
•
•
CH1 CH2
V
N
CH3
IEC 61000−4−2 ESD Requirements
Channel Loading Capacitance of 1.6 pF Typical
Channel I/O to GND Capacitance Difference of 0.04 pF Typical
Mutual Capacitance of 0.13 pF Typical
Minimal Capacitance Change with Temperature and Voltage
Each I/O Pin Can Withstand Over 1000 ESD Strikes
SOIC and MSOP Packages
These Devices are Pb−Free and are RoHS Compliant
CM1216−06SM
CM1216−06MR
CH8
CH7
V
P
CH6 CH5
CH1
CH2
CH3 CH4
V
N
CM1216−08MR
MARKING DIAGRAM
XXXXXX
A
Y
WW
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
Applications
•
IEEE1394 Firewire
®
Ports at 400 Mbps / 800 Mbps
•
DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
LCD Displays
•
Serial ATA Ports in Desktop PCs and Hard Disk Drives
•
PCI Express Ports
•
General Purpose High−Speed Data Line ESD Protection
XXXXX
AYWWG
G
ORDERING INFORMATION
Device
CM1216−06SM
CM1216−06MR
CM1216−08MR
Package
SOIC
(Pb−Free)
MSOP
(Pb−Free)
MSOP
(Pb−Free)
Shipping
†
2500/Tape & Reel
4000/Tape & Reel
4000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2011
February, 2011
−
Rev. 3
1
Publication Order Number:
CM1216/D
CM1216
PACKAGE / PINOUT DIAGRAMS
Top View
Top View
CH1
CH2
V
N
CH3
1
2
3
4
8
7
6
5
CH6
V
P
CH5
CH4
CH1
CH2
V
N
CH3
E166
Top View
1
2
3
4
8
7
6
5
CH6
V
P
CH5
CH4
E166
CH1
CH2
CH3
CH4
V
N
1
2
3
4
5
10
9
8
7
6
CH8
CH7
V
P
CH6
CH5
8−Pin SOIC−8
8−Pin MSOP−8
10−Pin MSOP−10
E168
Table 1. PIN DESCRIPTIONS
Pin Name
MSOP−8
Pin No.
CH1
CH2
CH3
CH4
V
N
CH5
CH6
V
P
CH7
CH8
1
2
4
5
3
6
8
7
−
−
SOIC−8
Pin No.
1
2
4
5
3
6
8
7
−
−
MSOP−10
Pin No.
1
2
3
4
5
6
7
8
9
10
I/O
I/O
I/O
I/O
GND
I/O
I/O
PWR
I/O
I/O
ESD Channel
ESD Channel
ESD Channel
ESD Channel
Negative voltage supply rail
ESD Channel
ESD Channel
Positive voltage supply rail
ESD Channel
ESD Channel
Type
Description
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Supply Voltage (V
P
−V
N
)
Diode Forward DC Current
DC Voltage at any Channel Input
Operating Temperature Range
Ambient
Junction
Storage Temperature Range
Rating
6
20
(V
N
−0.5)
to (V
P
+0.5)
−40
to +85
−40
to +125
−40
to +150
Units
V
mA
V
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Temperature Range (Ambient)
Package Power Rating
MSOP8 Package (CM1216−06MR)
SOIC8 Package (CM1216−06SM)
MSOP10 Package (CM1216−08MR)
Rating
−40
to +85
400
600
400
Units
°C
mW
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2
CM1216
Table 4. ELECTRICAL OPERATING CHARACTERISTICS
(Note 1)
Symbol
V
P
I
P
V
F
Parameter
Operating Supply Voltage
(V
P
−V
N
)
Operating Supply Current
Diode Forward Voltage
Top Diode
Bottom Diode
Channel Leakage Current
Channel Input Capacitance
Channel Input Capacitance Matching
Mutual Capacitance
ESD Protection
Peak Discharge Voltage at any
channel input, in system,
contact discharge per
IEC 61000−4−2 standard
Channel Clamp Voltage
Positive Transients
Negative Transients
Dynamic Resistance
Positive transients
Negative transients
(V
P
−V
N
) = 3.3 V
T
A
= 25°C
(Notes 2 and 3)
(V
P
−V
N
) = 3.3 V
Conditions
Min
Typ
3.3
Max
5.5
8
Units
V
mA
V
I
F
= 20
mA;
T
A
= 25°C
0.6
0.6
0.8
0.8
±0.1
1.6
0.04
0.13
0.95
0.95
±1.0
2.0
I
LEAK
C
IN
DC
IN
C
MUTUAL
V
ESD
T
A
= 25°C; V
P
= 5 V, V
N
= 0 V
At 1 MHz, V
P
= 3.3 V, V
N
= 0 V, V
IN
= 1.65 V
(Note 2)
mA
pF
pF
pF
kV
±15
V
CL
I
PP
= 1 A, t
P
= 8/20
mS;
T
A
= 25°C
+9.0
−1.5
0.6
0.4
V
R
DYN
I
PP
= 1 A, t
P
= 8/20
mS;
T
A
= 25°C
W
1. All parameters specified at T
A
=
−40°C
to +85°C unless otherwise noted.
2. Standard IEC 61000−4−2 with C
Discharge
= 150 pF, R
Discharge
= 330
W
, V
P
= 3.3 V, V
N
grounded.
3. From I/O pins to V
P
or V
N
only. V
P
bypassed to V
N
with low ESR 0.2
mF
ceramic capacitor.
PERFORMANCE CHARACTERISTICS
Figure 1. Typical Variation of C
IN
vs. V
IN
(f = 1 MHz, V
P
= 3.3 V, V
N
= 0 V, 0.1
mF
Chip Capacitor between V
P
and V
N
, T
A
= 255C)
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3
CM1216
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically
a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground,
which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power
supply is represented by L
1
and L
2
. The voltage V
CL
on the line being protected is:
V
CL
= Fwd voltage drop of D
1
+ V
SUPPLY
+ L
1
x d(I
ESD
) / dt + L
2
x d(I
ESD
) / dt
where I
ESD
is the ESD current pulse, and V
SUPPLY
is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(I
ESD
)/dt can be
approximated by
DI
ESD
/Dt, or 30/(1x10
−9
). So just 10 nH of series inductance (L
1
and L
2
combined) will lead to a 300 V
increment in V
CL
!
Similarly for negative ESD pulses, parasitic series inductance from the V
N
pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
The CM1213 has an integrated Zener diode between V
P
and V
N
. This greatly reduces the effect of supply rail inductance
L
2
on V
CL
by clamping V
P
at the breakdown voltage of the Zener diode. However, for the lowest possible V
CL
, especially when
V
P
is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22
μF
ceramic chip
capacitor be connected between V
P
and the ground plane.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V
P
pin of the Protection
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also ON Semiconductor Application Note, “Design Considerations for ESD Protection”, in the Applications section.
L
1
POSITIVE SUPPLY
PATH OF ESD CURRENT PULSE (IESD)
D
1
C
1
ONE
CHANNEL
LINE BEING
PROTECTED
CHANNEL
INPUT
SYSTEM OR
CIRCUITRY
D
2
BEING
PROTECTED
GROUND RAIL
CHASSIS GROUND
Figure 2. Application of Positive ESD Pulse between Input Channel and Ground
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4
CM1216
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC−01
ISSUE B
2X
D
A
8
5
0.10 C A-B
D
DETAIL A
EXPOSED
PAD
5
F
8
2X
0.10 C D
PIN ONE
LOCATION
0.10 C
8X
A2
A
0.10 C
SEATING
PLANE
GAUGE
PLANE
b1
L
(L1)
DETAIL A
q
C
SIDE VIEW
A1
0.25
c1
SECTION A−A
SOLDERING FOOTPRINT*
2.72
0.107
1.52
0.060
Exposed
Pad
7.0
0.275
2.03
0.08
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
ÇÇ
ÉÉ
ÇÇ
ÉÉ
ÇÇ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
1
E1
E
2X
4
8X
G
h
4
1
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS (ANGLES
IN DEGREES).
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
DIM
A
A1
A2
b
b1
c
c1
D
E
E1
e
L
L1
F
G
h
q
MILLIMETERS
MIN
MAX
1.35
1.75
0.00
0.10
1.35
1.65
0.31
0.51
0.28
0.48
0.17
0.25
0.17
0.23
4.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
0.40
1.27
1.04 REF
2.24
3.20
1.55
2.51
0.25
0.50
0
_
8
_
0.20 C
b
0.25 C A-B D
H
e
BOTTOM VIEW
B
TOP VIEW
A
A
END VIEW
c
(b)
嵌入式系统
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