PROTECTION PRODUCTS
Description
RailClamps are surge rated diode arrays designed to
protect high speed data interfaces. The SR series has
been specifically designed to protect sensitive compo-
nents which are connected to data and transmission
lines from overvoltage caused by electrostatic dis-
charge
(ESD),
electrical fast transients
(EFT),
and
tertiary
lightning.
The unique design of the SR series devices incorpo-
rates four surge rated, low capacitance steering diodes
and a TVS diode in a single package. The TVS diode is
constructed using Semtech’s proprietary low voltage
EPD technology for superior electrical characteristics at
3.3 volts.
During transient conditions, the steering diodes direct
the transient to either the positive side of the power
supply line or to ground. The internal TVS diode pre-
vents over-voltage on the power line, protecting any
downstream components.
The low capacitance array configuration allows the user
to protect two high-speed data or transmission lines.
The low inductance construction minimizes voltage
overshoot during high current surges.
RailClamp
Low Capacitance TVS Diode Array
Features
ESD protection to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
Array of surge rated diodes with internal
EPD TVS diode
Protects two I/O lines
Low capacitance (<10pF) for high-speed interfaces
Low leakage current (< 1µA)
Low operating voltage: 3.3V
Solid-state technology
SR3.3
Mechanical Characteristics
JEDEC SOT-143 package
Molding compound flammability rating: UL 94V-0
Marking : R3.3
Packaging : Tape and Reel
Applications
Data and I/O lines
Sensitive Analog Inputs
Video Line Protection
Portable Electronics
Microcontroller Input Protection
WAN/LAN Equipment
Circuit Diagram
Pin 4
Schematic & PIN Configuration
4
1
Pin 2
Pin 3
2
3
Pin 1
SOT-143 (Top View)
Revision 01/16/08
1
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SR3.3
PROTECTION PRODUCTS
Absolute Maximum Rating
R ating
Peak Pulse Power (tp = 8/20µs)
Peak Pulse Current (tp = 8/20µs)
Peak Forward Voltage (I
F
= 1A, tp=8/20µs)
Lead Soldering Temperature
Operating Temperature
Storage Temperature
Symbol
P
p k
I
P P
V
FP
T
L
T
J
T
STG
Value
150
10
1.5
260 (10 sec.)
-55 to +125
-55 to +150
Units
Watts
A
V
°C
°C
°C
Electrical Characteristics
SR 3.3
Parameter
Reverse Stand-Off Voltage
Punch-Through Voltage
Snap-Back Voltage
Reverse Leakage Current
Clamping Voltage
Clamping Voltage
Junction Capacitance
Symbol
V
RWM
V
PT
V
SB
I
R
V
C
V
C
C
j
I
PT
= 2µA
I
SB
= 50mA
V
RWM
= 3.3V, T=25°C
I
PP
= 1A, tp = 8/20µs
I
PP
= 10A, tp = 8/20µs
Between I/O pins and
Ground
V
R
= 0V, f = 1MHz
Between I/O pins
V
R
= 0V, f = 1MHz
6
3.5
2.8
1
7
15
10
Conditions
Minimum
Typical
Maximum
3.3
Units
V
V
V
µA
V
V
pF
3
pF
2008 Semtech Corp.
2
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SR3.3
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
Peak Pulse Power - P
Pk
(kW)
Power Derating Curve
110
100
% of Rated Power or
PP
I
90
80
70
60
50
40
30
20
10
1
0.1
0.01
0.1
1
10
Pulse Duration - tp (µs)
100
1000
0
0
25
50
75
100
125
150
Ambient Temperature - T
A
(
o
C)
Pulse Waveform
110
100
90
80
Percent of I
PP
70
60
50
40
30
20
10
0
0
5
10
15
Time (µs)
20
25
30
td = I
PP
/2
e
-t
Clamping Voltage vs. Peak Pulse Current
Waveform
Parameters:
tr = 8
µ
s
td = 20
µ
s
16
14
Clamping Voltage - V
C
(V)
12
10
8
6
4
2
0
0
2
4
6
8
10
12
Peak Pulse Current - I
PP
(A)
Waveform
Parameters:
tr = 8µs
td = 20µs
Line-To-Line
Line-To-Ground
Forward Voltage vs. Forward Current
10
9
Forward Voltage - V
F
(V)
8
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
40
45
50
Forward Current - I
F
(A)
Waveform
Parameters:
tr = 8µs
td = 20µs
2008 Semtech Corp.
3
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SR3.3
PROTECTION PRODUCTS
Applications Information
Device Connection Options for Protection of
Tw o High-Speed Data Lines
The SR3.3 TVS is designed to protect two data lines
from transient over-voltages by clamping them to a
fixed reference. When the voltage on the protected
line exceeds the reference voltage (plus diode V
F
) the
steering diodes are forward biased, conducting the
transient current away from the sensitive circuitry.
Data lines are connected at pins 2 and 3. The nega-
tive reference (REF1) is connected at pin 1. This pin
should be connected directly to a ground plane on the
board for best results. The path length is kept as short
as possible to minimize parasitic inductance.
The positive reference (REF2) is connected at pin 4.
The options for connecting the positive reference are
as follows:
Note that pins 4 is connected internally to the cathode
of the low voltage TVS. It is not recommended that this
pin be directly connected to a DC source greater than
the snap-back votlage (V
SB
) as the device can latch on
as described below.
EPD TVS Characteristics
These devices are constructed using Semtech’s
proprietary EPD technology. By utilizing the EPD tech-
nology, the SR3.3 can effectively operate at 3.3V while
maintaining excellent electrical characteristics.
The EPD TVS employs a complex nppn structure in
contrast to the pn structure normally found in tradi-
tional silicon-avalanche TVS diodes. Since the EPD
TVS devices use a 4-layer structure, they exhibit a
slightly different IV characteristic curve when compared
to conventional devices. During normal operation, the
device represents a high-impedance to the circuit up to
the device working voltage (V
RWM
). During an ESD
event, the device will begin to conduct and will enter a
low impedance state when the punch through voltage
(V
PT
) is exceeded. Unlike a conventional device, the low
voltage TVS will exhibit a slight negative resistance
characteristic as it conducts current. This characteris-
tic aids in lowering the clamping voltage of the device,
but must be considered in applications where DC
voltages are present.
When the TVS is conducting current, it will exhibit a
slight “snap-back” or negative resistance
2008 Semtech Corp.
4
I
PT
V
BRR
I
R
V
RWM
V V V
C
SB
PT
Pro
Internal
Data Line Pr o t ection Using Int ernal T V S Diode
as Reference
I
PP
I
SB
I
BRR
Figure 1 - EPD TVS IV Characteristic Curve
characteristics due to its structure. This point is
defined on the curve by the snap-back voltage (V
SB
)
and snap-back current (I
SB
). To return to a non-
conducting state, the current through the device must
fall below the I
SB
(approximately <50mA) and the
voltage must fall below the V
SB
(normally 2.8 volts for a
3.3V device). If a 3.3V TVS is connected to 3.3V DC
source, it will never fall below the snap-back voltage of
2.8V and will therefore stay in a conducting state.
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SR3.3
PROTECTION PRODUCTS
Applications Information
(continued)
Board Layout Considerations for ESD Protection
Board layout plays an important role in the suppression
of extremely fast rise-time ESD transients. Recall that
the voltage developed across an inductive load is
proportional to the time
PIN Descriptions
rate of change of current
through the load (V = L di/dt). The total clamping
voltage seen by the protected load will be the sum of
the TVS clamping voltage and the voltage due to the
parasitic inductance (V
C(TOT)
= V
C
+ L di/dt) .
Parasitic
inductance in the protection path can result in signifi-
cant voltage overshoot, reducing the effectiveness of
the suppression circuit.
An ESD induced transient for
example reaches a peak in approximately 1ns. For a
30A pulse (per IEC 61000-4-2 Level 4), 1nH of series
inductance will increase the effective clamping voltage
by 30V
(V = 1x10
-9
(30/1x10
-9
)). For maximum effectiveness,
the following board layout guidelines are recom-
mended:
Minimize the path length between the SR3.3 and
the protected line.
Place the SR3.3 near the RJ45 connector to
restrict transient coupling in nearby traces.
Minimize the path length (inductance) between the
RJ45 connector and the SR3.3.
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
2008 Semtech Corp.
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