PROTECTION PRODUCTS
Description
RailClamps are surge rated diode arrays designed to
protect high speed data interfaces. The SR12 has been
specifically designed to protect sensitive components
which are connected to data and transmission lines from
overvoltages caused by
ESD
(electrostatic discharge),
EFT
(electrical fast transients), and
lightning.
The unique design of the SR12 incorporates four surge
rated, low capacitance steering diodes and a TVS diode
in a single package. During transient conditions, the
steering diodes direct the transient to either the positive
side of the power supply line or to ground. The internal
TVS diode prevents over-voltage on the power line,
protecting any downstream components.
The low capacitance array configuration allows the user
to protect two high-speed data or transmission lines.
The low inductance construction minimizes voltage
overshoot during high current surges.
RailClamp
Low Capacitance TVS Diode Array
Features
Transient protection for high speed data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 0.5kV, 12A (8/20µs)
Array of surge rated diodes with internal TVS Diode
Protects two I/O lines
Operating Voltage: 12 volts
Low capacitance (5pF typical) for high-speed
interfaces
Low clamping voltage
Solid-state silicon-avalanche technology
SR12
Mechanical Characteristics
JEDEC SOT-143 package
UL 497B listed
Molding compound flammability rating: UL 94V-0
Marking : R12
Packaging : Tape and Reel per EIA 481
RoHS/WEEE Compliant
Applications
ADSL
Industrial Electronics
RS-422 Interfaces
Portable Electronics
Microcontroller Input Protection
WAN/LAN Equipment
Circuit Diagram
Pin 4
Schematic & PIN Configuration
1
Pin 2
Pin 3
4
2
Pin 1
3
SOT-143 (Top View)
Revision 04/11/05
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SR12
PROTECTION PRODUCTS
Absolute Maximum Rating
Rating
Peak Pulse Power (tp = 8/20µs)
Peak Pulse Current (tp = 8/20µs)
Peak Forward Voltage (I
F
= 1A, tp=8/20µs)
Lead Soldering Temperature
Operating Temperature
Storage Temperature
Symbol
P
pk
I
PP
V
FP
T
L
T
J
T
STG
Value
500
16
1.5
260 (10 sec.)
-55 to +125
-55 to +150
Units
Watts
A
V
°C
°C
°C
Electrical Characteristics
SR12
Parameter
Reverse Stand-Of f Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage
Clamping Voltage
Junction Capacitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
C
j
I
t
= 1mA
V
RWM
=12V, T=25°C
I
PP
= 5A, tp = 8/20µs
I
PP
= 16A, tp = 8/20µs
Between I/O pins and
Ground
V
R
= 0V, f = 1MHz
Between I/O pins
V
R
= 0V, f = 1MHz
5
13.3
1
24
31
10
Conditions
Minimum
Typical
Maximum
12
Units
V
V
µA
V
V
pF
3
pF
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SR12
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
(kW)
110
100
% of Rated Power or
PP
I
90
80
70
60
50
40
30
20
10
0
Power Derating Curve
PP
Peak Pulse Power - P
1
0.1
0.01
0.1
1
10
Pulse Duration - tp (µs)
100
1000
0
25
50
75
100
o
125
150
Ambient Temperature - T
A
( C)
Pulse Waveform
110
100
90
80
Percent of I
PP
70
60
50
40
30
20
10
0
0
5
10
15
Time (µs)
20
25
30
td = I
PP
/2
e
-t
Clamping Voltage vs. Peak Pulse Current
33
Waveform
Parameters:
tr = 8µs
td = 20µs
30
(V)
Clamping Voltage - V
C
27
24
21
18
15
12
9
6
3
0
0
4
8
12
16
20
Peak Pulse Current - I
R
(A)
Waveform
Parameters:
tr = 8µs
td = 20µs
Forward Voltage vs. Forward Current
10
9
Forward Voltage - V
F
(V)
8
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
40
45
50
Forward Current - I
F
(A)
Waveform
Parameters:
tr = 8
µ
s
td = 20
µ
s
% Change in Capacitance
0
-2
-4
-6
-8
-10
-12
-14
-16
0
Capacitance vs. Reverse Voltage
1
2
3
4
5
6
Reverse Voltage - V
R
(V)
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SR12
PROTECTION PRODUCTS
Applications Information
Device Connection Options for Protection of Two
High-Speed Data Lines
The SR12 TVS is designed to protect two data lines from
transient over-voltages by clamping them to a fixed
reference. When the voltage on the protected line
exceeds the reference voltage (plus diode V
F
) the steering
diodes are forward biased, conducting the transient
current away from the sensitive circuitry.
Data lines are connected at pins 2 and 3. The nega-
tive reference (REF1) is connected at pin 1. This pin
should be connected directly to a ground plane on the
board for best results. The path length is kept as short
as possible to minimize parasitic inductance.
The positive reference (REF2) is connected at pin 4.
The options for connecting the positive reference are
as follows:
1. To protect data lines and the power line, connect
pin 4 directly to the positive supply rail (V
CC
). In this
configuration the data lines are referenced to the
supply voltage. The internal TVS diode prevents
over-voltage on the supply rail.
2. The SR12 can be isolated from the power supply by
adding a series resistor between pin 4 and V
CC
. A
value of 10kΩ is recommended. The internal TVS
and steering diodes remain biased, providing the
advantage of lower capacitance.
3. In applications where no positive supply reference
is available, or complete supply isolation is desired,
the internal TVS may be used as the reference. In
this case, pin 4 is not connected. The steering
diodes will begin to conduct when the voltage on
the protected line exceeds the working voltage of
the TVS (plus one diode drop).
ESD Protection With RailClamps
RailClamps are optimized for ESD protection using the
rail-to-rail topology. Along with good board layout,
these devices virtually eliminate the disadvantages of
using discrete components to implement this topology.
Consider the situation shown in Figure 1 where dis-
crete diodes or diode arrays are configured for rail-to-
rail protection on a high speed line. During positive
duration ESD events, the top diode will be forward
biased when the voltage on the protected line exceeds
the reference voltage plus the V
F
drop of the diode.
Data Line and Power Supply Protection Using Vcc as
reference
Data Line Protection with Bias and Power Supply
Isolation Resistor
Data Line Protection Using Internal TVS Diode as
Reference
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SR12
PROTECTION PRODUCTS
Applications Information
(continued)
For negative events, the bottom diode will be biased
when the voltage exceeds the V
F
of the diode. At first
approximation, the clamping voltage due to the charac-
teristics of the protection diodes is given by:
V
C
= V
CC
+ V
F
(for positive duration pulses)
PIN Descriptions
(for negative duration pulses)
V
C
= -V
F
However, for fast rise time transient events, the
effects of parasitic inductance must also be consid-
ered as shown in Figure 2. Therefore, the actual
clamping voltage seen by the protected circuit will be:
V
C
= V
CC
+ V
F
+ L
P
di
ESD
/dt (for positive duration pulses)
V
C
= -V
F
- L
G
di
ESD
/dt
(for negative duration pulses)
ESD current reaches a peak amplitude of 30A in 1ns
for a level 4 ESD contact discharge per IEC 1000-4-2.
Therefore, the voltage overshoot due to 1nH of series
inductance is:
V = L
P
di
ESD
/dt = 1X10
-9
(30 / 1X10
-9
) = 30V
Example:
Consider a V
CC
= 5V, a typical V
F
of 30V (at 30A) for the
steering diode and a series trace inductance of 10nH.
The clamping voltage seen by the protected IC for a
positive 8kV (30A) ESD pulse will be:
V
C
= 5V + 30V + (10nH X 30V/nH) = 335V
This does not take into account that the ESD current is
directed into the supply rail, potentially damaging any
components that are attached to that rail. Also note
that it is not uncommon for the V
F
of discrete diodes to
exceed the damage threshold of the protected IC. This
is due to the relatively small junction area of typical
discrete components. It is also possible that the
power dissipation capability of the discrete diode will
be exceeded, thus destroying the device.
The RailClamp is designed to overcome the inherent
disadvantages of using discrete signal diodes for ESD
suppression. The RailClamp’s integrated TVS diode
helps to mitigate the effects of parasitic inductance in
Figure 2 - The Effects of Parasitic Inductance
When Using Discrete Components to Implement
Rail- To-Rail Pr o t ection
Rail-T
Pro
“Rail-T
Pro
Topology
Figure 1 - “Rail-To-Rail” Pr o t ection Topology
(First Approximation)
Rail-T
Pro
Figure 3 - Rail- To-Rail Pr o t ection Using
RailClamp
Arrays
RailClam p T V S Arra ys
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