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TMC2272A
Digital Colorspace Converter
36 Bit Color, 50 MHz
Features
• 50 MHz (20ns) pipelined throughput
• 3 Simultaneous 12-bit input and output channels
(64 Giga {236} colors)
• Two's complement inputs and outputs
• Overflow headroom available in lower resolution
• 10-bit user-defined coefficients
• TTL compatible input and output signals
• Full precision internal calculation
• Output rounding
• On-board coefficient memory
• Submicron CMOS process
Applications
• Translation between component color standards (RGB,
YIQ, YUV, etc.)
• Broadcast composite color encoding and decoding (all
standards)
• Broadcast composite color standards conversion and
transcoding
• Camera tube and monitor phosphor colorimetry
correction
• White balancing and color-temperature conversion
• Image capture, processing and storage
• Color matching between systems, cameras and monitors
• Three-dimensional perspective translation
Description
A 50-MHz, three-channel, 36 bit (three 12-bit components)
colorspace converter and color corrector, the TMC2272A
uses 9 parallel multipliers to process high-resolution imagery
in real time.
The TMC2272A also operates at any slower clock rate and
with any smaller data path width, allowing it to handle all
broadcast and consumer camera, frame-grabber, encoder/
decoder, recorder and monitor applications as well as most
electronic imaging applications.
A complete set of three 12-bit samples is processed on every
clock cycle, with a five-cycle pipeline latency. Full 23-bit
(for each of three components) internal precision is provided
with 10-bit user-defined coefficients. The coefficients may be
varied dynamically, with three new coefficients loaded every
clock cycle. (The full set of nine can be replaced in three clock
cycles.) Rounding to 12 bits per component is performed only
at the final output. This allows full accuracy with correct
rounding and overflow headroom for applications that require
less than 12 bits per component.
The TMC2272A is fabricated in a submicron CMOS process
and performance is guaranteed over the full operating tem-
perature range. It is available in a 120-pin Plastic Pin Grid
Array (PPGA) package, 120-pin Ceramic Pin Grid Array
(CPGA), 120-pin MQFP to PGA package, and 120-pin
Plastic Quad FlatPack (PQFP) in three speed grades.
Logic Symbol
CLK
Data Input
A
11-0
B
11-0
C
11-0
KA
11-0
KB
11-0
KC
11-0
Y
11-0
Coefficient
Input
Z
11-0
Data Output
X
11-0
TMC2272A
Colorspace Converter
CSEL
1-0
REV. 1.1.3 10/25/00
PRODUCT SPECIFICATION
TMC2272A
Block Diagram
CWSEL1,0
A11-0
DECODER
2
1
12
CWSEL1,0 = 0 1
ENABLE K_X
CWSEL1,0 = 1 0
ENABLE K_Y
CWSEL1,0 = 1 1
ENABLE K_Z
2
ENA
KAX
10
3
4
KA9-0
10
10
21
10
12
ENA
KAY
10
2
12
ENA
KAZ
21
3
4
10
10
2
12
21
3
4
B11-0
12
1
2
ENA
KBX
10
3
4
10
21
10
3
4
12
ENA
KBY
10
21
10
3
4
2
12
ENA
KBZ
10
21
2
12
KB9-0
10
C11-0
1
12
2
ENA
KCX
10
3
4
10
21
10
3
4
12
ENA
KCY
10
21
10
3
4
2
12
ENA
KCZ
10
21
2
12
KC9-0
10
(ROUND)
12
CLK
5
12
X11-0
(ROUND)
12
5
12
Y11-0
(ROUND)
12
5
12
Z11-0
2
REV. 1.1.3 10/25/00
TMC2272A
PRODUCT SPECIFICATION
Functional Description
The TMC2272A is a nine–multiplier array with the internal bus
structure and summing adders needed to implement a 3 x 3
matrix multiplier (triple dot product). With a 50MHz guaran-
teed maximum clock rate, this device offers video and imaging
system designers a single–chip solution to numerous common
image and signal–processing problems.
The three data input ports (A
11-0
, B
11-0
, C
11-0
) accept 12-bit
two's complement integer data, which is also the format for
the output ports (X
11-0
, Y
11-0
, Z
11-0
). Other format and path
width options are discussed in the numeric format and over-
flow section. The coefficient input ports (KA, KB, KC) are
always 10-bit two's complement fractional. Table
2
details
the bit weighting.
Full precision is maintained throughout the TMC2272A.
Each output is accurately rounded to 12 bits from the 23 bits
entering the final adder.
KAX(n) thru KCZ(n)
Indicates coefficient value stored in the specified
one of the nine onboard coefficient registers
KAX through KCZ, input during or before the
specified clock rising edge (n).
X(n), Y(n), Z(n)
Indicates data available at that output port t
DO
after the specified clock rising edge (n).
Applies to output ports X
11-0
, Y
11-0
, and Z
11-0
.
The TMC2272A utilizes six input and output ports to realize
a "triple dot product", in which each output is the sum of all
three input words, multiplied by the appropriate stored coef-
ficients. The three corresponding sums of products are avail-
able at the outputs five clock cycles after the input data are
latched, and three new data words rounded to 12-bits are then
available every clock cycle. See the Applications Discussion
regarding encoded video standard conversion matrices.
X(5)=A(1)KAX(1)+B(1)KBX(1)+C(1)KCX(1)
Y(5)=A(1)KAY(1)+B(1)KBY(1)+C(1)KCY(1)
Z(5)=A(1)KAZ(1)+B(1)KBZ(1)+C(1)KCZ(1)
Signal Definitions
A(n), B(n), C(n)
Indicates the data word presented to that input
port during the specified clock rising edge (n).
Applies to input ports A
11-0
, B
11-0
, and C
11-0
.
Pin Assignments
120 Pin Plastic Pin Grid Array, H5 Package, 120 Pin Ceramic Pin Grid Array, G1 Package, and
120 Pin MQFP to PPGA, H6 Package
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M N
KEY
Top View
Cavity Up
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
C1
C2
C3
C4
Name
X7
X9
X10
GND
C11
C8
C7
C5
C3
C1
B10
B7
B4
X4
X5
X8
X11
GND
C9
C6
C4
C2
B11
B9
B6
B2
X1
X2
X6
VDD
Pin
C5
C6
C7
C8
C9
C10
C11
C12
C13
D1
D2
D3
D11
D12
D13
E1
E2
E3
E11
E12
E13
F1
F2
F3
F11
F12
F13
G1
G2
G3
Name
GND
C10
GND
VDD
C0
B8
B5
B3
B1
Y11
X0
X3
CLK
B0
A10
Y9
Y10
GND
A11
A9
A8
Y7
Y8
VDD
A7
A6
A5
Y5
Y6
GND
Pin
G11
G12
G13
H1
H2
H3
H11
H12
H13
J1
J2
J3
J11
J12
J13
K1
K2
K3
K11
K12
K13
L1
L2
L3
L4
L5
L6
L7
L8
L9
Name
A3
A2
A4
Y4
Y0
VDD
GND
A0
A1
Y1
Y2
GND
KA8
CWSEL1
CWSEL0
Y3
Z0
Z3
KA4
KA7
KA9
Z1
Z4
Z6
GND
KC0
GND
VDD
KB0
KB4
Pin
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
Name
KB8
KA1
KA5
KA6
Z2
Z7
Z9
Z11
KC2
KC4
KC6
KC9
KB2
KB5
KB9
KA2
KA3
Z5
Z8
Z10
KC1
KC3
KC5
KC7
KC8
KB1
KB3
KB6
KB7
KA0
REV. 1.1.3 10/25/00
3
PRODUCT SPECIFICATION
TMC2272A
Pin Assignments
(continued)
120 Pin Metric Quad Flat Pack (MQFP), KE Package
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Name
X6
X5
X4
X3
X2
X1
X0
GND
Y11
Y10
Y9
VDD
Y8
Y7
Y6
GND
Y5
Y4
Y0
VDD
Y1
Y2
Y3
GND
Z0
Z1
Z2
Z3
Z4
Z5
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
Z6
Z7
Z8
GND
Z9
Z10
Z11
KC0
KC1
KC2
KC3
GND
KC4
KC5
KC6
VDD
KC7
KC8
KC9
KB0
KB1
KB2
KB3
KB4
KB5
KB6
KB7
KB8
KB9
KA0
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Name
KA1
KA2
KA3
KA4
KA5
KA6
KA7
KA8
KA9
CWSEL1
CWSEL0
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B0
B1
B2
CLK
B3
B4
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Name
B5
B6
B7
B8
B9
B10
B11
C0
C1
C2
C3
VDD
C4
C5
C6
GND
C7
C8
C9
C10
C11
GND
GND
GND
X11
X10
X9
VDD
X8
X7
1
120
91
90
30
31
61
60
Pin Descriptions
Pin Name
Power
V
DD
GND
F3, H3, L7, C8, 12, 20, 46, 102,
C4
118
E3, G3, J3, L4, 8, 16, 24, 34, 42,
L6, H11, C7, C5, 72, 106, 112,
A4, B5
113, 114
D11
88
Supply Voltage.
The TMC2272A operates from a single +5V
supply. All pins must be connected.
Ground
CPGA/PPGA/
MPGA
Pin Number
KE Pin Number
Pin Function Description
Clock
CLK
System Clock.
The TMC2272A operates from a single system
clock input. All timing specifications are referenced to the rising
edge of clock.
Coefficient Write Select.
This input selects which three of the 9
coefficient registers, if any, will be updated on the next clock
cycle from the KA
9-0
, KB
9-0
, AND KC
9-0
inputs. See Table 4 and
the Functional Block Diagram.
Controls
CWSEL
1,0
J12, J13
70, 71
4
REV. 1.1.3 10/25/00
TMC2272A
PRODUCT SPECIFICATION
Pin Descriptions
(continued)
Pin Name
Inputs
A
11-0
E11, D13, E12,
E13, F11, F12,
F13, G13, G11,
G12, H13, H12
B10, A11, B11,
C10, A12, B12,
C11, A13, C12,
B13, C13, D12
A5, C6, B6, A6,
A7, B7, A8, B8,
A9, B9, A10, C9
K13, J11, K12,
L13, L12, K11,
M13, M12, L11,
N13
M11, L10, N12,
N11, M10, L9,
N10, M9, N9, L8
84, 83, 82, 81,
80, 79, 78, 77,
76, 75, 74, 73
97, 96, 95, 94,
93, 92, 91, 90,
89, 87, 86, 85
111, 110, 109,
108, 107, 105,
104, 103, 101,
100, 99, 98
69, 68, 67, 66,
65, 64, 63, 62,
61, 60
Data Input A.
This is one of three 12-bit wide data input ports.
CPGA/PPGA/
MPGA
Pin Number
KE Pin Number
Pin Function Description
B
11-0
Data Input B.
This is one of three 12-bit wide data input ports.
C
11-0
Data Input C.
This is one of three 12-bit wide data input ports.
KA
9-0
Coefficient Input KAX, KAY, or KAZ.
These are the 10-bit
wide coefficient input ports. The value at each of these three
inputs will update one coefficient register as selected by the
coefficient write select (CWSEL
1-0
) on the next clock. See Table
1 and the Functional Block Diagram.
Coefficient Input KBX, KBY, OR KBZ.
These are the 10-bit
wide coefficient input ports. The value at each of these three
inputs will update one coefficient register as selected by the
coefficient write select (CWSEL
1-0
) on the next clock. See Table
1 and the Functional Block Diagram.
Coefficient Input KCX, KCY, OR KCZ.
These are the 10-bit
wide coefficient input ports. The value at each of these three
inputs will update one coefficient register as selected by the
coefficient write select (CWSEL
1-0
) on the next clock. See Table
1 and the Functional Block Diagram.
Output X.
These are the data outputs. Data are available at the
12-bit registered Output Ports X,Y and Z t
DO
after every clock
rising edge.
Output Y.
These are the data outputs. Data are available at the
12-bit registered Output Ports X,Y and Z t
DO
after every clock
rising edge.
Output Z.
These are the data outputs. Data are available at the
12-bit registered Output Ports X,Y and Z t
DO
after every clock
rising edge.
KB
9-0
59, 58, 57, 56,
55, 54, 53, 52,
51, 50
KC
9-0
M8, N8, N7, M7,
N6, M6, N5, M5,
N4, L5
49, 48, 47, 45,
44, 43, 41, 40,
39, 38
Outputs
X
11-0
B4, A3, A2, B3, 115, 116, 117,
A1, C3, B2, B1, 119, 120, 1, 2, 3,
D3, C2, C1, D2
4, 5, 6, 7
D1, E2, E1, F2, 9, 10, 11, 13, 14,
F1, G2, G1, H1, 15, 17, 18, 23,
K1, J2, J1, H2
22, 21, 19
M4, N3, M3, N2,
M2, L3, N1, L2,
K3, M1, L1, K2
37, 36, 35, 33,
32, 31, 30, 29,
28, 27, 26, 25
Y
11-0
Z
11-0
Table 1. Coefficient Loading
CWSEL
1,0
00
Hold
All
Hold
All
Hold
All
01
Load
KAX
Load
KBX
Load
KCX
10
Load
KAY
Load
KBY
Load
KCY
11
Load
KAZ
Load
KBZ
Load
KCZ
Input
Input
Input
KA
9-0
KB
9-0
KC
9-0
REV. 1.1.3 10/25/00
5
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