VERSA
Datasheet Rev 1.3
VRS700
VERSA 700: 64kB FLASH, 4kB RAM
23MHz, 3V, 8-Bit MCU
Datasheet Rev 1.3
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
1
VERSA
Datasheet Rev 1.3
VRS700
Overview
The VRS700 is a 3V, 8-bit microcontroller with 64kB of
Flash memory and 4K RAM that is based on the
architecture of the standard 80C51 microcontroller
family. It is pin compatible with these devices.
Among the VRS700’s features are 8 PWM outputs, a
Watch Dog Timer, bank mapping to permit direct
addressing of the 4096 bytes of RAM and a serial port.
The VRS700’s hardware features and powerful
instruction set make it a versatile and cost-effective
controller for a wide range of applications requiring a
microcontroller running at 3V.
The Flash memory can be programmed using
programmers available from Goal Semiconductor or
other 3
rd
party commercial programmers.
The VRS700 is available in PLCC-44 and QFP-44
packages in the Industrial Temperature Range.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Operating voltage: 3.0V ~ 3.6V
General 80C51/80C52 family compatible
64kB on-chip Flash memory
4096 bytes on-chip data RAM
Bank mapping direct addressing mode to access RAM
Four 8-bit I/O ports + one 4-bit I/O port
8-Channel PWM on P1.0~P1.7
Full duplex serial port (UART)
Three 16-bit Timers/Counters
Watch Dog Timer
8-bit Unsigned Multiply and Division Instructions
BCD arithmetic
Direct and Indirect Addressing
Two levels of Interrupt Priority and Nested Interrupts
Power saving modes
Code protection functions
Operates at a clock frequency from 3MHz to 23MHz
Low EMI (inhibit ALE)
Industrial Temperature Range (-40ºC to +85ºC)
F
IGURE
2: VRS700 PLCC-44
AND
QFP-44 P
IN OUT
D
IAGRAMS
PWM4/P1.4
PWM3/P1.3
PWM2/P1.2
PWM1/T2EX/P1.1
PWM0/T2/P1.0
P4.2
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
F
IGURE
1: VRS700 B
LOCK
D
IAGRAM
8051
PROCESSOR
64kx8
FLASH
4096 Bytes of
RAM
ADDRESS/
DATA BUS
PWM5/P1.5
6
7
40
39
1
P0.3/AD3
PORT 0
8
PWM6/P1.6
PWM7/P1.7
RES
RXD/P3.0
P4.3
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
PORT 1
8
VRS700
PLCC-44
P0.4/AD4
P0.5/AD5
P0.7/AD7
P0.6/AD6
#EA
P4.1
ALE
#PSEN
P2.7/A15
UART
PORT 2
8
T0/P3.4
T1/P3.5
17
18
28
29
P2.6/A14
P2.5/A13
#WR/P3.6
#RD/P3.7
XTAL2
XTAL1
VSS
P4.0
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P0.7/AD7
#EA
P4.1
ALE
P2.7/A15
#PSEN
TIMER 0
TIMER 1
TIMER 2
RESET
POWER
CONTROL
WATCHDOG
TIMER
P0.4/AD4
P0.5/AD5
P0.6/AD6
PWM
8
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
P4.2
SPWM0/T2/P1.0
SPWM1/T2EX/P1.1
SPWM2/P1.2
SPWM3/P1.3
SPWM4/P1.4
44
34
33
P2.6/A14
P2.5/A13
23
22
PORT 4
4
P2.4/A12
2 INTERRUPT
INPUTS
PORT 3
8
P2.4/A12
P2.3/A11
P2.2/A10
VRS700
QFP-44
P2.1/A9
P2.0/A8
P4.0
VSS
XTAL1
XTAL2
12
11
1
#RD/P3.7
#WR/P3.6
SPWM7/P1.7
RE
S
RXD/P3.0
SPWM5/P1.5
SPWM6/P1.6
P4.3
TXD/P3.1
#INT0/P3.2
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
#INT1/P3.3
T0/P3.4
T1/P3.5
2
VERSA
Datasheet Rev 1.3
VRS700
Pin Descriptions for QFP-44/PLCC-44
T
ABLE
1: P
IN
D
ESCRIPTIONS FOR
QFP-44/PLCC-44
QFP
- 44
PLCC
- 44
Name
I/O
Function
QFP
- 44
PLCC
- 44
Name
I/O
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
SPWM5
P1.5
SPWM6
P1.6
SPWM7
P1.7
RES
RXD
P3.0
P4.3
TXD
P3.1
#INT0
P3.2
#INT1
P3.3
T0
P3.4
T1
P3.5
#WR
P3.6
#RD
P3.7
XTAL2
XTAL1
VSS
P4.0
P2.0
A8
P2.1
A9
P2.2
A10
P2.3
A11
P2.4
A12
P2.5
A13
O
I/O
O
I/O
O
I/O
I
I
I/O
I/O
O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
O
I/O
O
I/O
O
I
-
I/O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
SPWM Channel 5
Bit 5 of Port 1
SPWM Channel 6
Bit 6 of Port 1
SPWM Channel 7
Bit 7 of Port 1
Reset
Receive Data
Bit 0 of Port 3
Bit 3 of Port 4
Transmit Data &
Bit 1 of Port 3
Low True Interrupt 0
Bit 2 of Port 3
Low True Interrupt 1
Bit 3 of Port 3
Timer 0
Bit 4 of Port 3
Timer 1 & 3
Bit 5 of Port 3
Ext. Memory Write
Bit 6 of Port 3
Ext. Memory Read
Bit 7 of Port 3
Oscillator/Crystal Output
Oscillator/Crystal In
Ground
Bit 0 of Port 4
Bit 0 of Port 2
Bit 8 of External Memory Address
Bit 1 of Port 2
Bit 9 of External Memory Address
Bit 2 of Port 2
Bit 10 of External Memory Address
Bit 3 of Port 2 &
Bit 11 of External Memory Address
Bit 4 of Port 2
Bit 12 of External Memory Address
Bit 5 of Port 2
Bit 13 of External Memory Address
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
P2.6
A14
P2.7
A15
#PSEN
ALE
P4.1
#EA
P0.7
AD7
P0.6
AD6
P0.5
AD5
P0.4
AD4
P0.3
AD3
P0.2
AD2
P0. 1
AD1
P0.0
AD0
VDD
P4.2
T2
P1.0
SPWM0
T2EX
P1.1
SPWM1
P1.2
SPWM2
P1.3
SPWM3
P1.4
SPWM4
I/O
O
I/O
O
O
O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
I
I/O
O
I
I/O
O
I/O
O
I/O
O
I/O
O
Bit 6 of Port 2
Bit 14 of External Memory Address
Bit 7 of Port 2
Bit 15 of External Memory Address
Program Store Enable
Address Latch Enable
Bit 1 of Port 4
External Access
Bit 7 Of Port 0
Data/Address Bit 7 of External Memory
Bit 6 of Port 0
Data/Address Bit 6 of External Memory
Bit 5 of Port 0
Data/Address Bit 5 of External Memory
Bit 4 of Port 0
Data/Address Bit 4 of External Memory
Bit 3 Of Port 0
Data/Address Bit 3 of External Memory
Bit 2 of Port 0
Data/Address Bit 2 of External Memory
Bit 1 of Port 0 & Data
Address Bit 1 of External Memory
Bit 0 Of Port 0 & Data
Address Bit 0 of External Memory
VCC
Bit 2 of Port 4
Timer 2 Clock Out
Bit 0 of Port 1
SPWM Channel 0
Timer 2 Control
Bit 1 of Port 1
SPWM Channel 1
Bit 2 of Port 1
SPWM Channel 2
Bit 3 of Port 1
SPWM Channel 3
Bit 4 of Port 1
SPWM Channel 4
SPWM1/T2E X/P1.1
SPWM0/T2/P 1.0
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
#PSEN
P2.7/A15
P2.6/A14
P2.5/A13
SPWM4/P1.4
SPWM3/P1.3
SPWM2/P1.2
P4.1
ALE
#EA
P0.0/AD0
P0.1/AD1
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
P4.2
SPWM0/T2/P1.0
SPWM1/T2EX/P1.1
SPWM2/P1.2
SPWM3/P1.3
SPWM4/P1.4
33 32 31 30 29 28 27 26 25 24 23
34
22
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
7
8
21
20
19
18
17
16
15
14
13
12
9 10 11
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
P4.0
VSS
XTAL1
XTAL2
#RD/P3.7
#WR/P3.6
6
5
4
3
2
SPWM5/P1.5
SPWM6/P1.6
SPWM7/P1.7
RES
RXD/P3.0
P4.3
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
7
8
9
10
11
12
13
14
15
16
17
1 4 4 43 42 41 40
39
38
37
36
P0.2/AD2
P4.2
VDD
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
#EA
P4.1
ALE
#PSEN
P2.5/A13
P2.6/A14
P2.7/A15
VRS700L
QFP-44
VRS700L
PLCC-44
35
34
33
32
31
30
29
18 1 9 20 2 1 2 2 23 2 4 25 26 27 28
RES
SPWM5/P1.5
SPWM6/P1.6
SPWM7/P1.7
#INT0/P3.2
#INT1/P3.3
RXD/P3.0
TXD/P3.1
T0/P3.4
T1/P3.5
P4.3
#RD/P3.7
XTAL2
XTAL1
VSS
P2.1/A9
P2.2/A10
P2.3/A11
#WR/P3.6
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
P 2.4/A12
P4.0
P2.0/A8
3
VERSA
Datasheet Rev 1.3
Instr. Cycles
1
1
1
1
1
1
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
VRS700
Instruction Set
All VRS700 instructions are binary code compatible and
perform the same functions as the industry standard 8051.
The following two tables describe the instruction set of the
VRS700.
T
ABLE
2: L
EGEND FOR
I
NSTRUCTION
S
ET
T
ABLE
Symbol
A
Rn
Direct
@Ri
rel
bit
#data
#data 16
addr 16
addr 11
Function
Accumulator
Register R0-R7
Internal register address
Internal register pointed to by R0 or R1 (except MOVX)
Two' complement offset byte
s
Direct bit address
8-bit constant
16-bit constant
16-bit destination address
11-bit destination address
Mnemonic
CPL A
SWAP A
RL A
RLC A
RR A
RRC A
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
Size
(bytes)
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
MOV direct, @Ri
Instr. Cycles
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
MOV @Ri, #data
MOV DPTR, #data
MOVC A, @A+DPTR
Description
Compliment A
Sw ap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
Move register to A
Move direct byte to A
Move data memory to A
Move immediate to A
Move A to register
Move direct byte to register
Move immediate to register
Move A to direct byte
Move register to direct byte
Move direct byte to direct byte
Move data memory to direct byte
Move immediate to direct byte
Move A to data memory
Move direct byte to data memory
Move immediate to data memory
Move immediate to data pointer
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (A8) to A
Move external data (A16) to A
Move A to external data (A8)
Move A to external data (A16)
Push direct byte onto stack
Pop direct byte from stack
Exchange A and register
Exchange A and direct byte
Exchange A and data memory
Exchange A and data memory nibble
Absolute call to subroutine
Long call to subroutine
Return from subroutine
Return from interrupt
Absolute jump unconditional
Long jump unconditional
Short jump (relative address)
Jump on carry = 1
Jump on carry = 0
Jump on direct bit = 1
Jump on direct bit = 0
Jump on direct bit = 1 and clear
Jump indirect relative DPTR
Jump on accumulator = 0
Jump on accumulator 1= 0
Compare A, direct JNE relative
Compare A, immediate JNE relative
Compare reg, immediate JNE relative
Compare ind, immediate JNE relative
Decrement register, JNZ relative
Decrement direct byte, JNZ relative
No operation
Size
(bytes)
1
1
1
1
1
1
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
2
3
1
1
2
3
2
2
2
3
3
3
1
2
2
3
3
3
3
2
3
1
Data Transfer Instructions
T
ABLE
3: VERSA 700 I
NSTRUCTION
S
ET
Mnemonic
Description
Arithmetic instructions
Add register to A
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @ Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
Logical Instructions
ANL A, Rn
ANL A, direct
ANL A, @ Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
XRL direct, #data
CLR A
Add direct byte to A
Add data memory to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add data memory to A w ith carry
Add immediate to A w ith carry
Subtract register from A w ith borrow
Subtract direct byte from A w ith borrow
Subtract data mem from A w ith borrow
Subtract immediate from A w ith borrow
Increment A
Increment register
Increment direct byte
Increment data memory
Decrement A
Decrement register
Decrement direct byte
Decrement data memory
Increment data pointer
Multiply A by B
Divide A by B
Decimal adjust A
AND register to A
AND direct byte to A
AND data memory to A
AND immediate to A
AND A to direct byte
AND immediate data to direct byte
OR register to A
OR direct byte to A
OR data memory to A
OR immediate to A
OR A to direct byte
OR immediate data to direct byte
Exclusive-OR register to A
Exclusive-OR direct byte to A
Exclusive-OR data memory to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Exclusive-OR immediate to direct byte
Clear A
MOVC A, @A+PC
MOVX A, @Ri
MOVX A, @DPTR
MOVX @Ri, A
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
Branching Instructions
ACALL addr 11
LCALL addr 16
RET
RETI
AJMP addr 11
LJMP addr 16
SJMP rel
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A
, direct, rel
CJNE A, #d, rel
CJNE Rn, #d, rel
CJNE @ Ri, #d, rel
DJNZ Rn, rel
DJNZ direct, rel
NOP
Miscellaneous Instruction
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
4
VERSA
Datasheet Rev 1.3
VRS700
Special Function Registers (SFR)
Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table
lists the VRS700 Special Function Registers.
T
ABLE
4: S
PECIAL
F
UNCTION
R
EGISTERS
(SFR)
SFR
Register
P0
SP
DPL
DPH
(Reserved)
RCON
DBANK
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
P1
WDTKEY
SCON
SBUF
SPWME
WDTC
P2
IE
P3
SPWMD0
SPWMD1
SPWMD2
SPWMD3
IP
SPWMD4
SPWMD5
SPWMD6
SPWMD7
SCONF
T2CON
T2MOD
RCAP2L
RCAP2H
TL2
TH2
PSW
SPWMC0
SPWMC1
SPWMC2
SPWMC3
P4
SPWMC4
SPWMC5
SPWMC6
SPWMC7
ACC
B
SFR
Adrs
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
90h
97h
98h
99h
9Bh
9Fh
A0h
A8h
B0h
B3h
B4h
B5h
B6h
B8h
BBh
BCh
BDh
BEh
BFh
C8h
C9h
CAh
CBh
CCh
CDh
D0h
D3h
D4h
D5h
D6h
D8h
DBh
DCh
DDh
DEh
E0h
F0h
Bit 7
-
-
-
-
-
BSE
SMOD
TF1
GATE1
-
-
-
-
-
WDTKEY7
SM0
-
SPWM7E
WDTE
-
EA
-
-
-
-
-
-
-
-
-
-
WDR
TF2
-
-
-
-
CY
-
-
-
-
-
Bit 6
-
-
-
-
-
-
-
TR1
C/T1
-
-
-
-
-
WDTKEY6
SM1
-
SPWM6E
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EXF2
-
-
-
-
AC
-
-
-
-
-
Bit 5
-
-
-
-
-
BS5
-
TF0
M1.1
-
-
-
-
-
WDTKEY5
SM2
-
SPWM5E
CLEAR
-
ET2
-
-
-
-
-
PT2
-
-
-
-
-
RCLK
-
-
-
-
F0
-
-
-
-
-
Bit 4
-
-
-
-
-
BS4
-
TR0
M0.1
-
-
-
-
-
WDTKEY4
REN
-
SPWM4E
-
-
ES
-
-
-
-
-
PS
-
-
-
-
-
TCLK
-
-
-
-
RS1
-
-
-
-
-
Bit 3
-
-
-
-
RAMS3
BS3
GF1
IE1
GATE0
-
-
-
-
-
WDTKEY3
TB8
-
SPWM3E
-
-
ET1
-
-
-
-
-
PT1
-
-
-
-
-
EXEN2
-
-
-
-
RS0
-
-
-
-
P4.3
Bit 2
-
-
-
-
RAMS2
BS2
GF0
IT1
C/T0
-
-
-
-
-
WDTKEY2
RB8
-
SPWM2E
PS2
-
EX1
-
-
-
-
-
PX1
-
-
-
-
TR2
-
-
-
-
OV
PBS0
PBS1
PBS2
PBS3
P4.2
PBS4
PBS5
PBS6
PBS7
-
-
Bit 1
-
-
-
-
RAMS1
BS1
PDOWN
IE0
M1.0
-
-
-
-
-
WDTKEY1
TI
-
SPWM1E
PS1
-
ET0
-
-
-
-
-
PT0
-
-
-
-
OME
C/T2
T2OE
-
-
-
-
PFS01
PFS11
PFS21
PFS31
P4.1
PFS41
PFS51
PFS61
PFS71
-
-
Bit 0
-
-
-
-
RAMS0
BS0
IDLE
IT0
M0.0
-
-
-
-
-
WDTKEY0
RI
-
SPWM0E
PS0
-
EX0
-
-
-
-
-
PX0
-
-
-
-
ALEI
CP/RL2
DCEN
-
-
-
P
PFS00
PFS10
PFS20
PFS30
P4.0
PFS40
PFS50
PFS60
PFS70
-
-
Reset
Value
00000000b
0***0001b
00000000b
00000000b
00000000b
********b
00000000b
00000000b
0*0**000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
0****00b
00000000b
00000000b
-
-
-
-
-
-
-
-
-
-
******00b
******00b
******00b
******00b
****1111b
******00b
******00b
******00b
******00b
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