S E M I C O N D U C T O R
HSP3824
Direct Sequence Spread Spectrum
Baseband Processor
TM
PRELIMINARY
March 1996
Features
• Complete DSSS Baseband Processor
• High Data Rate. . . . . . . . . . . . . . . . . . . . .up to 4 MBPS
• Processing Gain . . . . . . . . . . . . . . . . . . . . . up to 12dB
• Programmable PN Code . . . . . . . . . . . . up to 16 Bits
• Ultra Small Package . . . . . . . . . . . . . . . . . 7 x 7 x 1mm
• Single Supply Operation (33MHz Max) . . 2.7V to 5.5V
• Single Supply Operation (44MHz Max) . . 3.3V to 5.0V
• Modulation Method . . . . . . . . . . . . . DBPSK or DQPSK
• Supports Full or Half Duplex Operations
• On-Chip A/D Converters for I/Q Data (3-Bit, 44 MSPS)
and RSSI (6-Bit, 2 MSPS)
Description
The Harris HSP3824 Direct
Sequence (DSSS) baseband pro-
cessor is part of the PRISM™
2.4GHz radio chipset, and contains
all the functions necessary for a full or half duplex packet base-
band transceiver.
The HSP3824 has on-board ADC’s for analog I and Q inputs, for
which the HFA3724 IF QMODEM is recommended. Differential
phase shift keying modulation schemes DBPSK and DQPSK,
with optional data scrambling capability, are combined with a pro-
grammable PN sequence of up to 16 bits. Built-in flexibility allows
the HSP3824 to be configured through a general purpose control
bus, for a wide range of applications. A Receive Signal Strength
Indicator (RSSI) monitoring function with on-board 6-bit 2 MSPS
ADC provides Clear Channel Assessment (CCA) to avoid data
collisions and optimize network throughput. The HSP3824 is
housed in a thin plastic quad flat package (TQFP) suitable for
PCMCIA board applications.
Applications
• Systems Targeting IEEE802.11 Standard
• DSSS PCMCIA Wireless Transceiver
• Spread Spectrum WLAN RF Modems
• TDMA Packet Protocol Radios
• Part 15 Compliant Radio Links
• Portable Bar Code Scanners/POS Terminal
• Portable PDA/Notebook Computer
• Wireless Digital Audio
• Wireless Digital Video
• PCN/Wireless PBX
Ordering Information
PART NO.
HSP3824VI
TEMP. RANGE
-40
o
C to +85
o
C
PKG. TYPE
48 Lead TQFP
PKG. NO.
Q48.7x7
Simplified Block Diagram
Pinout
I
OUT
Q
OUT
HSP3824 (TQFP)
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
TEST1
TEST0
V
DD
GND
I
IN
DE-SPREADER
3-BIT
A/D
DATA TO NETWORK
PROCESSOR
DPSK
DEMOD.
Q
IN
3-BIT
A/D
TEST_CK
TX_PE
TXD
TXCLK
TX_RDY
GND
V
DD
R/W
CS
V
DD
GND
1
2
3
4
5
6
7
8
9
10
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
RXCLK
RXD
MD_RDY
RX_PE
CCA
GND
MCLK
V
DD
RESET
ANTSEL
A/D_CAL
SD
RSSI
6-BIT
A/D
CCA
PRO-
CESSOR
INTER-
FACE
CTRL
I
OUT
SPREADER
Q
OUT
DPSK
MOD.
I
IN
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
GND
V
REFP
V
REFN
GND
V
DD
SCLK
V
DD
RSSI
V
DD
GND
Q
IN
AS
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1996
1
PRISM™ and the PRISM™ logo are Trademarks of Harris Corporation
File Number
4064.2
HSP3824
List of Contents
Typical Application Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TX Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RX Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
I/Q ADC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ADC Calibration Circuit and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
RSSI ADC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Test Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
External AGC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Transmitter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Header/Packet Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PN Generator Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Scrambler and Data Encoder Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Modulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Clear Channel Assessment (CCA) and Energy Detect (ED) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Receiver Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Acquisition Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Two Antenna Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
One Antenna Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Acquisition Signal Quality Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Procedure to Set Acq. Signal Quality Parameters (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PN Correlator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Data Demodulation and Tracking Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Procedure to Set Signal Quality Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Data Decoder and Descrambler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Demodulator Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Overall Eb/N0 Versus BER Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clock Offset Tracking Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Carrier Offset Frequency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
I/Q Amplitude Imbalance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
A Default Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
HSP3824 33MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
HSP3824 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
HSP3824 44MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Thin Plastic Quad Flatpack Packages (TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2
HSP3824
Typical Application Diagram
HFA3724
(FILE# 4067)
TUNE/SELECT
HSP3824
(FILE# 4064)
RXI
DATA TO MAC
CTRL
SPREAD
DPSK
MOD.
PRISM™ CHIP SET FILE #4063
HFA3424
(NOTE)
(FILE# 4131)
A/D
DE-
SPREAD
DPSK
DEMOD
HFA3624
RF/IF
CONVERTER
(FILE# 4066)
I
RXQ
A/D
CCA
802.11
MAC-PHY
INTERFACE
÷
2
0 /90
o
o
M
U
X
M
U
X
RSSI
A/D
TXI
RFPA
HFA3925
(FILE# 4132)
VCO
VCO
TXQ
Q
QUAD IF MODULATOR
DUAL SYNTHESIZER
DSSS BASEBAND PROCESSOR
HFA3524
(FILE# 4062)
TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HSP3824
NOTE: Required for systems targeting 802.11 specifications.
For additional information on the PRISM™ chip set, call
(407) 724-7800 to access Harris’ AnswerFAX system. When
prompted, key in the four-digit document number (File #) of
the datasheets you wish to receive.
The four-digit file numbers are shown in Typical Application
Diagram, and correspond to the appropriate circuit.
3
HSP3824
Pin Description
NAME
V
DD
(Analog)
V
DD
(Digital)
GND (Analog)
GND (Digital)
V
REFN
V
REFP
I
IN
Q
IN
RSSI
A/D_CAL
PIN
10, 18, 20
7, 21, 29, 42
11, 15, 19
6, 22, 31, 41
17
16
12
13
14
26
TYPE I/O
Power
Power
Ground
Ground
I
I
I
I
I
O
DC power supply 2.7V - 5.5V
DC power supply 2.7V - 5.5V
DC power supply 2.7V - 5.5V, ground.
DC power supply 2.7V - 5.5V, ground.
“Negative” voltage reference for ADC’s (I and Q) [Relative to V
REFP
]
“Positive” voltage reference for ADC’s (I, Q and RSSI)
Analog input to the internal 3-bit A/D of the In-phase received data.
Analog input to the internal 3-bit A/D of the Quadrature received data.
Receive Signal Strength Indicator Analog input.
This signal is used internally as part of the I and Q ADC calibration circuit. When the
ADC calibration circuit is active, the voltage references of the ADCs are adjusted to
maintain the outputs of the ADCs in their optimum range. A logic 1 on this pin indicates
that one or both of the ADC outputs are at their full scale value. This signal can be
integrated externally as a control voltage for an external AGC.
When active, the transmitter is configured to be operational, otherwise the transmitter
is in standby mode. TX_PE is an input from the external Media Access Controller
(MAC) or network processor to the HSP3824. The rising edge of TX_PE will start the
internal transmit state machine and the falling edge will inhibit the state machine.
TX_PE envelopes the transmit data.
TXD is an input, used to transfer serial Data or Preamble/Header information bits from
the MAC or network processor to the HSP3824. The data is received serially with the
LSB first. The data is clocked in the HSP3824 at the falling edge of TXCLK.
TXCLK is a clock output used to receive the data on the TXD from the MAC or network
processor to the HSP3824, synchronously. Transmit data on the TXD bus is clocked
into the HSP3824 on the falling edge. The clocking edge is also programmable to be
on either phase of the clock. The rate of the clock will be depending upon the
modulation type and data rate that is programmed in the signalling field of the header.
When the HSP3824 is configured to generate the preamble and Header information
internally, TX_RDY is an output to the external network processor indicating that
Preamble and Header information has been generated and that the HSP3824 is ready
to receive the data packet from the network processor over the TXD serial bus. The
TX_RDY returns to the inactive state when the TX_PE goes inactive indicating the end
of the data transmission. TX_RDY is an active high signal. This signal is meaningful
only when the HSP3824 generates its own preamble.
Clear Channel Assessment (CCA) is an output used to signal that the channel is clear
to transmit. The CCA algorithm is user programmable and makes its decision as a
function of RSSI, Energy detect (ED), Carrier Sense (CRS) and the CCA watch dog
timer. The CCA algorithm and its programmable features are described in the data
sheet.
Logic 0 = Channel is clear to transmit.
Logic 1 = Channel is NOT clear to transmit (busy).
NOTE: This polarity is programmable and can be inverted.
RXD is an output to the external network processor transferring demodulated Header
information and data in a serial format. The data is sent serially with the LSB first. The
data is frame aligned with MD_RDY.
RXCLK is the clock output bit clock. This clock is used to transfer Header information
and data through the RXD serial bus to the network processor. This clock reflects the
bit rate in use.RXCLK will be held to a logic “0” state during the acquisition process.
RXCLK becomes active when the HSP3824 enters in the data mode. This occurs once
bit sync is declared and a valid signal quality estimate is made, when comparing the
programmed signal quality thresholds.
DESCRIPTION
TX_PE
2
I
TXD
3
I
TXCLK
4
O
TX_RDY
5
O
CCA
32
O
RXD
35
O
RXCLK
36
O
4
HSP3824
Pin Description
NAME
MD_RDY
(Continued)
TYPE I/O
O
DESCRIPTION
MD_RDY is an output signal to the network processor, indicating a data packet is
ready to be transferred to the processor. MD_RDY is an active high signal and it
envelopes the data transfer over the RXD serial bus. MD_RDY returns to its inactive
state when there is no more receiver data, when the programmable data length
counter reaches its value or when the link has been interrupted. MD_RDY remains
inactive during preamble synchronization.
When active, receiver is configured to be operational, otherwise receiver is in standby
mode. This is an active high input signal.
The antenna select signal changes state as the receiver switches from antenna to
antenna during the acquisition process in the antenna diversity mode.
SD is a serial bi-directional data bus which is used to transfer address and data to/from
the internal registers. The bit ordering of an 8-bit word is MSB first. The first 8 bits
during transfers indicate the register address immediately followed by 8 more bits
representing the data that needs to be written or read at that register.
SCLK is the clock for the SD serial bus.The data on SD is clocked at the rising edge.
SCLK is an input clock and it is asynchronous to the internal master clock (MCLK)The
maximum rate of this clock is 10MHz or the master clock frequency, whichever is
lower.
AS is an address strobe used to envelope the Address or the data on SD.
Logic 1 = envelopes the address bits.
Logic 0 = envelopes the data bits.
R/W is an input to the HSP3824 used to change the direction of the SD bus when
reading or writing data on the SD bus. R/W must be set up prior to the rising edge of
SCLK. A high level indicates read while a low level is a write.
CS is a Chip select for the device to activate the serial control port.The CS doesn’t
impact any of the other interface ports and signals, i.e. the TX or RX ports and
interface signals. This is an active low signal. When inactive SD, SCLK, AS and R/W
become “don’t care” signals.
This is a data port that can be programmed to bring out internal signals or data for
monitoring. This data includes: Correlator phase and magnitude, NCO frequency
offset estimate, and signal quality estimates. Some of the discrete signals available
include: Carrier Sense (CRS), which becomes active when initial PN acquisition has
been declared. Energy Detect (ED) which becomes active when the integrated RSSI
value exceeds the programmable threshold. Both ED and CRS are active high
signals.These bits are primarily reserved by the manufacturer for testing. A further
description of the test port is given at the appropriate section of this data sheet.
This is the clock that is used in conjunction with the data that is being output from the
test bus (TEST 0-7).
Master reset for device. When active TX and RX functions are disabled. If RESET is
kept low the HSP3824 goes into the power standby mode. RESET does not alter any
of the configuration register values nor it presets any of the registers into default
values. Device requires programming upon power-up. RESET must be inactive during
programming of the device.
Master Clock for device. The maximum frequency of this clock is 44MHz. This is used
internally to generate all other internal necessary clocks and is divided by 1, 2, 4, or 8
for the transceiver clocks.
TX Spread baseband I digital output data. Data is output at the programmed chip rate.
TX Spread baseband Q digital output data. Data is output at the programmed chip
rate.
PIN
34
RX_PE
ANTSEL
SD
33
27
25
I
O
I/O
SCLK
24
I
AS
23
I
R/W
8
I
CS
9
I
TEST 0-7
37, 38, 39,
40, 43, 44,
45, 46
O
TEST_CK
RESET
1
28
O
I
MCLK
30
I
I
OUT
Q
OUT
48
47
O
O
NOTE: Total of 48 pins; ALL pins are used.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
