DATASHEET
MULTIPLIER AND ZERO DELAY BUFFER
Description
The MK2302-01 is a high performance Zero Delay Buffer
(ZDB) which integrates IDT’s proprietary analog/digital
Phase Locked Loop (PLL) techniques. The chip is part of
IDT’s ClockBlocks
TM
family and was designed as a
performance upgrade to meet today’s higher speed and
lower voltage requirements. The zero delay feature means
that the rising edge of the input clock aligns with the rising
edges of both output clocks, giving the appearance of no
delay through the device. There are two outputs on the chip,
one being a low-skew divide by two of the other output.
The MK2302-01 is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to graphics/video. By allowing off-chip
feedback paths, the device can eliminate the delay through
other devices.
MK2302-01
Features
•
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•
•
•
•
•
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8-pin SOIC package
Pb (lead) free package
Low input to output skew of 250 ps max
Absolute jitter ± 500 ps
Propagation Delay ± 350 ps
Ability to choose between different multipliers from 0.5X
to 16X
Output clock frequency up to 168 MHz at 3.3 V
Can recover degraded input clock duty cycle
Output clock duty cycle of 45/55
Full CMOS clock swings with 25mA drive capability at
TTL levels
Advanced, low power CMOS process
Operating voltage of 3.3 V or 5 V
Industrial temperature version available
Block Diagram
IC L K
S 1 :0
F B IN
d ivid e
by N
P h a se
D e te cto r,
C h a rg e
Pum p,
and Loop
F ilte r
VCO
/2
C LK1
C LK2
E xte rn a l fe e d b a ck ca n co m e fro m C L K 1 o r C L K 2 (se e ta b le o n p a g e 2 )
IDT™
MULTIPLIER AND ZERO DELAY BUFFER
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MK2302-01
REV G 051310
MK2302-01
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
Pin Assignment
FBIN
ICLK
GND
S0
1
2
3
4
8
7
6
5
CLK2
VDD
CLK1
S1
8 pin (150 mil) SOIC
Clock Multiplier Decoding Table 1
(Multiplies Input clock by shown amount)
FBIN
CLK1
CLK1
CLK1
CLK1
CLK2
CLK2
CLK2
CLK2
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
CLK1
2 X ICLK
4 X ICLK
ICLK
8 X ICLK
4 X ICLK
8 X ICLK
2 X ICLK
16 X ICLK
CLK2
ICLK
2 X ICLK
ICLK/2
4 X ICLK
2 X ICLK
4 X ICLK
ICLK
8 XICLK
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
FBIN
ICLK
GND
S0
S1
CLK1
VDD
CLK2
Pin
Type
Input
Input
Power
Input
Input
Output
Power
Output
Pin Description
Feedback clock input.
Reference clock input.
Connect to ground.
Select 0 for output clock per decoding table above. Pull-up.
Select 1 for output clock per decoding table above. Pull up.
Clock output per table above.
Connect to +3.3 V or +5.0 V.
Clock output per table above. Low skew divide by two of pin 6 clock.
IDT™
MULTIPLIER AND ZERO DELAY BUFFER
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MK2302-01
REV G 051310
MK2302-01
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
External Components
The MK2302-01 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be
connected close to the part to minimize lead inductance. No external power supply filtering is required for this
device. A 33Ω series terminating resistor can be used next to each output pin.
Using CLK1 as the feedback will always result in synchronized rising edges between ICLK and CLK1. However, the
CLK2 could be a falling edge compared with ICLK. IDT recommends using CLK2 feedback whenever possible. This
will synchronize the rising edges of all three clocks.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2302-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Power Dissipation
7V
Rating
-0.5 V to VDD+0.5 V
-55 to 125° C
-65 to +150° C
125° C
0.5 W
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
Power Supply Voltage (measured in respect to GND)
Min.
0
-40
+4.5
+3.15
Typ.
Max.
+70
+85
Units
°
C
°
C
V
V
+5.0
+3.3
+5.5
+3.45
IDT™
MULTIPLIER AND ZERO DELAY BUFFER
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MK2302-01
REV G 051310
MK2302-01
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
DC Electrical Characteristics
VDD = 3.3 V ±5%,
Ambient Temperature 0 to +70° C or -40° C to 85° C
Parameter
Operating Voltage
Operating Current
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
(mid-level)
Input Low Voltage
Output High Voltage
(CMOS High)
Output High Voltage
Output Low Voltage
Short Circuit Current
Input Capacitance
Symbol Conditions
VDD
IDD
V
IH
V
IL
V
IH
V
IM
V
IL
V
OH
V
OH
V
OL
I
OS
C
IN
ICLK, FBIN
ICLK, FBIN
S0, S1
S0, S1
S0, S1
I
OH
= -4 mA
I
OH
= -12 mA
I
OL
= 12 mA
Each output
S0, S1
Min.
3.15
Typ.
20
Max.
3.45
Units
V
ma
V
2
0.8
VDD-0.5
VDD/2
0.5
VDD-0.4
2.4
0.4
±70
5
V
V
V
V
V
V
V
mA
pF
VDD = 5 V ±10%,
Ambient Temperature 0 to +70° C or -40° C to 85° C
Parameter
Operating Voltage
Operating Current
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
(mid-level)
Input Low Voltage
Output High Voltage (CMOS
High)
Output High Voltage
Output Low Voltage
Short Circuit Current
Input Capacitance
Symbol Conditions
VDD
IDD
V
IH
V
IL
V
IH
V
IM
V
IL
V
OH
V
OH
V
OL
I
OS
C
IN
ICLK, FBIN
ICLK, FBIN
S0, S1
S0, S1
S0, S1
I
OH
= -4 mA
I
OH
= -12 mA
I
OL
= 12 mA
Each output
S0, S1
5V
Min.
4.5
Typ.
30
Max.
5.5
Units
V
ma
V
2
0.8
VDD-0.5
VDD/2
0.5
VDD-0.4
2.4
0.4
±100
5
V
V
V
V
V
V
V
mA
pF
IDT™
MULTIPLIER AND ZERO DELAY BUFFER
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MK2302-01
REV G 051310
MK2302-01
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
AC Electrical Characteristics
VDD = 3.3 V or 5 V ±5%,
Ambient Temperature 0 to +70° C or -40° C to 85° C
Parameter
Input Frequency, ICLK
Output Clock Frequency
Output to Output Skew
Input to Output Jitter
Input Skew
Symbol
Conditions
FBIN from CLK/2
CLK1
40 - 150 MHz
ICLK to FBIN,
CLK>30 MHz, Note 1
ICLK to FBIN,
CLK<30 MHz, Note 1
Min.
10
Typ.
Max. Units
168
MHz
ps
ps
ps
ps
ns
ns
%
See table on page 2
100
-300
-600
0.8
0.8
40
49 - 51
175
200
300
600
1
1
60
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
0.8 to 2.0 V, Note 2
2.0 to 0.8 V, Note 2
at VDD/2
Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2.
Note 2: Measured with 27Ω terminating resistor and 15 pF loads.
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
150
140
120
40
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
IDT™
MULTIPLIER AND ZERO DELAY BUFFER
5
MK2302-01
REV G 051310
嵌入式系统
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