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INTEGRATED CIRCUITS
74LVT162373
3.3 V LVT 16-bit transparent D-type latch
with 30
Ω
termination resistors (3-State)
Product specification
IC23 Data Handbook
1999 Sep 23
Philips
Semiconductors
Philips Semiconductors
Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30
Ω
termination resistors (3-State)
74LVT162373
FEATURES
•
16-bit transparent latch
•
3-State buffers
•
Output capability: +12 mA / –12 mA
•
TTL input and output switching levels
•
Input and output interface capability to systems at 5 V supply
•
Bus-hold data inputs eliminate the need for external pull-up
•
Live insertion/extraction permitted
•
Outputs include series resistance of 30
Ω
making external
•
Power-up reset
•
Power-up 3-State
•
No bus current loading when output is tied to 5 V bus
•
Latch-up protection exceeds 500 mA per JEDEC Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
resistors unnecessary
resistors to hold unused inputs
DESCRIPTION
The 74LVT162373 is a high-performance BiCMOS product designed
for V
CC
operation at 3.3 V.
This device is a 16-bit transparent D-type latch with non-inverting
3-State bus compatible outputs. The device can be used as two
8-bit latches or one 16-bit latch. When Latch Enable (LE) input is
High, the Q outputs follow the data (D) inputs. When Latch Enable is
taken Low, the Q outputs are latched at the levels of the D inputs
one setup time prior to the High-to-Low transition.
The 74LVT162373 is designed with 30
Ω
series resistance in both
the High and Low states of the output. This design reduces the
noise in applications such as memory address drivers, clock drivers,
and bus receivers/transmitters.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
nDx to nQx
Input capacitance
Output capacitance
Total supply current
C
L
= 50 pF;
V
CC
= 3.3 V
V
I
= 0 V or 3.0 V
Outputs disabled; V
O
= 0 V or 3.0 V
Outputs disabled; V
CC
= 3.6 V
CONDITIONS
T
amb
= 25
°C
TYPICAL
3.0
3
9
70
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40
°C
to +85
°C
–40
°C
to +85
°C
ORDERING CODE
74LVT162373 DL
74LVT162373 DGG
DWG NUMBER
SOT370-1
SOT362-1
1999 Sep 23
2
853-2172 22406
Philips Semiconductors
Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30
Ω
termination resistors (3-State)
74LVT162373
PIN CONFIGURATION
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
V
CC
2Q4
2Q5
GND
2Q6
2Q7
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1LE
1D0
1D1
GND
1D2
1D3
V
CC
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
V
CC
2D4
2D5
GND
2D6
2D7
2LE
LOGIC SYMBOL
47
46
44
43
41
40
38
37
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
48
1
1LE
1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
2
36
3
35
5
33
6
32
8
30
9
29
11
27
12
26
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7
25
24
2LE
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
13
14
16
17
19
20
22
23
SA00044
LOGIC SYMBOL (IEEE/IEC)
1OE
1LE
2OE
2LE
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
4D
2
∇
1EN
C3
2EN
C4
1
∇
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
SA00043
PIN DESCRIPTION
PIN NUMBER
47, 46, 44, 43, 41,
40, 38, 37, 36, 35,
33, 32, 30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11,
12, 13, 14, 16, 17,
19, 20, 22, 23
1, 24
48, 25
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42
SYMBOL
1D0 – 1D7
2D0 – 2D7
1Q0 – 1Q7
2Q0 – 2Q7
1OE, 2OE
1LE, 2LE
GND
V
CC
FUNCTION
Data inputs
1D1
1D2
1D3
1D4
1D5
1D6
3D
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
Data outputs
Output Enable inputs
(active-Low)
Latch Enable inputs
(active-High)
Ground (0V)
Positive supply voltage
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
SW00010
1999 Sep 23
3
Philips Semiconductors
Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30
Ω
termination resistors (3-State)
74LVT162373
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
D
D
D
D
D
D
D
D
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
nLE
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
SA00046
FUNCTION TABLE
INPUTS
nOE
L
L
L
L
L
H
H
H =
h =
L =
l =
NC=
X =
Z =
↓
=
nLE
H
H
↓
↓
L
L
H
nDx
L
H
l
h
X
X
nDx
INTERNAL
REGISTER
L
H
L
H
NC
NC
nDx
OUTPUTS
OPERATING MODE
nQ0 – nQ7
L
H
L
H
NC
Z
Z
Enable and read register
Latch and read register
Hold
Disable outputs
High voltage level
High voltage level one set-up time prior to the High-to-Low E transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low E transition
No change
Don’t care
High impedance “off ” state
High-to-Low LE transition
SCHEMATIC OF EACH OUTPUT
V
CC
27
Ω
OUTPUT
27
Ω
SW00503
1999 Sep 23
4
FPGA/CPLD
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