Si53019-A 01A
19 -O
U T P U T
PCI
E
G
E N
3 B
U F F E R
Features
Nineteen 0.7 V current-mode,
HCSL PCIe Gen 3 outputs
100 MHz /133 MHz PLL
operation, supports PCIe and
QPI
PLL bandwidth SW SMBUS
programming overrides the latch
value from HW pin
9 selectable SMBus addresses
Fixed external feedback path
8 dedicated OE pin
PLL or bypass mode
Spread spectrum tolerable
50 ps output-to-output skew
Fixed 0 ps input to output delay
Low phase jitter (Intel QPI, PCIe
Gen 1/Gen 2/Gen 3/Gen 4
common clock compliant
Gen 3 SRNS Compliant
100 ps input-to-output delay
Extended Temperature:
–40 to 85 °C
Package: 72-pin QFN
Ordering Information:
See page 32.
Applications
Server
Storage
Data Center
Network Security
Pin Assignments
Description
The Si53019-A01A is a 19-output, current mode HCSL differential clock
buffer that meets all of the performance requirements of the Intel
DB1900Z specification. The device is optimized for distributing reference
clocks for Intel
®
QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/
Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel
SMI) applications. The VCO of the device is optimized to support
100 MHz and 133 MHz operation. Each differential output can be enabled
through I
2
C for maximum flexibility and power savings. Measuring PCIe
clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool.
Download it for free at
www.silabs.com/pcie-learningcenter.
Patents pending
Rev. 1.5 7/17
Copyright © 2017 by Silicon Laboratories
Si53019-A01A
Si53019- A01A
Functional Block Diagram
2
Rev. 1.5
Si5301 9-A01 A
T
A B L E
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1. CLK_IN, CLK_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2. 100M_133M—Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.3. SA_0, SA_1—Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.4. CKPWRGD/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.5. HBW_BYPASS_LBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.6. Miscellaneous Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.1. Input Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.2. Termination of Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1. Byte Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.2. Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5. Pin Descriptions: 72-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Power Filtering Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6.1. Ferrite Bead Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
9.1. 10x10 mm 72-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Rev. 1.5
3
Si53019- A01A
1. Electrical Specifications
Table 1. DC Operating Characteristics
1
V
DD_A
= 3.3 V±5%, V
DD
= 3.3 V±5%
Parameter
3.3 V Core Supply Voltage
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input Leakage Current
2
3.3 V Input High Voltage
3
3.3 V Input Low Voltage
3
3.3 V Input Low Voltage
3.3 V Input Med Voltage
3.3 V Input High Voltage
3.3 V Output High Voltage
4
3.3 V Output Low Voltage
4
Input Capacitance
5
Output Capacitance
5
Pin Inductance
Ambient Temperature
Symbol
VDD/VDD_A
V
IH
V
IL
I
IL
V
IH_FS
V
IL_FS
V
IL_Tri
V
IM_Tri
V
IH_Tri
V
OH
V
OL
C
IN
C
OUT
L
PIN
T
A
Test Condition
3.3 V ±5%
V
DD
0 < VIN < V
DD
V
DD
Min
3.135
2.0
VSS–0.3
–5
0.7
VSS–0.3
0
1.3
2.4
Max
3.465
V
DD
+0.3
0.8
+5
V
DD
+0.3
0.35
0.9
1.8
V
DD
—
0.4
4.5
4.5
7
85
Unit
V
V
V
μA
V
V
V
V
V
V
V
pF
pF
nH
°C
I
OH
= –1 mA
I
OL
= 1 mA
2.4
—
2.5
2.5
—
No Airflow
–40
Notes:
1.
VDD_IO applies to the low-power NMOS push-pull HCSL compatible outputs.
2.
Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state
current requirements.
3.
Internal voltage reference is to be used to guarantee V
IH
_FS and V
IL
_FS thresholds levels over full operating range.
4.
Signal edge is required to be monotonic when transitioning through this region.
5.
Ccomp capacitance based on pad metallization and silicon device capacitance. Not including pin capacitance.
4
Rev. 1.5
Si5301 9-A01 A
Table 2. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)
1
Parameter
Clock Stabilization Time
2
Long Term Accuracy
3,4,5
Absolute Host CLK Period (100 MHz)
3,4,6
Absolute Host CLK Period (133 MHz)
3,4,6
Slew Rate
3,4,7
Slew Rate Matching
3,8,10,11
Rise Time Variation
3,8,9
Fall Time Variation
3,8,9
Voltage High (typ 0.7 V)
3,8,12
Voltage Low (typ 0.7 V)
3,8,13
Symbol
CLK 100 MHz, 133 MHz
Min
T
STAB
L
ACC
T
ABS
T
ABS
Edge_rate
T
RISE_MAT
/
T
FALL_MAT
∆
Trise
∆
Tfall
V
HIGH
V
LOW
—
—
9.94900
7.44925
1.0
—
—
—
660
–150
3.0
7
—
—
750
15
Typ
1.5
—
—
Max
1.8
100
10.05100
7.55075
4.0
20
125
125
850
150
ms
ppm
ns
ns
V/ns
%
ps
ps
mV
mV
Unit
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8–2.0 V to the
time that stable clocks are output from the buffer chip (PLL locked).
3.
Test configuration is Rs = 33.2
,
Rp = 49.9, 2 pF for 100
transmission line; Rs = 27
,
Rp = 42.2, 2 pF for 85
transmission line.
4.
Measurement taken from differential waveform.
5.
Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are
99,750,00 Hz, 133,000,000 Hz.
6.
The average period over any 1
μs
period of time must be greater than the minimum and less than the maximum
specified period.
7.
Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from –150 mV
to +150 mV on the differential waveform. Scope is set to average because the scope sample clock is making most of
the dynamic wiggles along the clock edge Only valid for Rising CLOCK and Falling CLOCK. Signal must be monotonic
through the Vol to Voh region for Trise and Tfall.
8.
Measurement taken from single-ended waveform.
9.
Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
10.
Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of clock verses the
falling edge rate (average) of CLOCK.
11.
Rise/Fall matching is derived using the following, 2*(Trise - Tfall) / (Trise + Tfall).
12.
VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.
13.
VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.
14.
Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of
CLK.
15.
This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is
crossing.
16.
The crossing point must meet the absolute and relative crossing point specifications simultaneously.
17.
Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg – 0.700), Vcross(rel)
Max = 0.550 – 0.5 (0.700 – Vhavg), (see Figure 4–5 for further clarification).
18.
Vcross
is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK. This is the
maximum allowed variance in Vcross for any particular system.
19.
Overshoot is defined as the absolute value of the maximum voltage.
20.
Undershoot is defined as the absolute value of the minimum voltage.
Rev. 1.5
5
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