MT9J003
MT9J003 1/2.3‐Inch 10 Mp
CMOS Digital Image Sensor
General Description
The ON Semiconductor MT9J003 is a 1/2.3-inch CMOS
active-pixel digital imaging sensor with an active pixel array of 3856
(H) x 2764 (V) including border pixels. It can support 10 megapixel
(3664 (H) x 2748 (V)) digital still images and a 1080 p (3840 (H) x
2160 (V)) digital video mode. It incorporates sophisticated on-chip
camera functions such as windowing, mirroring, column and row skip
modes, and snapshot mode. It is programmable through a simple
two-wire serial interface and has very low power consumption.
The MT9J003 digital image sensor features ON Semiconductor’s
breakthrough low-noise CMOS imaging technology that achieves
near-CCD image quality (based on signal-to-noise ratio and low-light
sensitivity) while maintaining the inherent size, cost, and integration
advantages of CMOS.
When operated in its default 4:3 still-mode, the sensor generates a
full resolution image at 15 frames per second (fps) using the HiSPi
serial interface. An on-chip analog-to-digital converter (ADC)
generates a 12-bit value for each pixel.
Features
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ILCC48 10x10
CASE 847AK
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
•
•
•
•
•
•
•
•
•
•
•
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1080p Digital Video Mode
Simple Two-wire Serial Interface
Auto Black Level Calibration
Support for External Mechanical Shutter
Support for External LED or Xenon Flash
High Frame Rate Preview Mode with Arbitrary Down-size Scaling
from Maximum Resolution
Programmable Controls: Gain, Horizontal and Vertical Blanking,
Auto Black Level Offset Correction, Frame Size/rate, Exposure,
Left–right and Top–bottom Image Reversal, Window Size, and
Panning
Data Interfaces: Parallel or Four-lane Serial High-speed Pixel
Interface (HiSPi) Differential Signaling (Sub-LVDS)
On-die Phase-locked Loop (PLL) Oscillator
Bayer Pattern Downsize Scaler
Integrated Position-based Color and Lens Shading Correction
One-time Programmable Memory (OTPM) for Storing Module
Information
Applications
•
Digital Video Cameras
•
Digital Still Cameras
©
Semiconductor Components Industries, LLC, 2009
February, 2017
−
Rev. 5
1
Publication Order Number:
MT9J003/D
MT9J003
Table 1. KEY PARAMETERS
Parameter
Optical Format
Active Imager Size
1/2.3-inch (4:3)
6.440 mm (H) x 4.616 mm (V), 7.923 mm Diagonal (Entire Sensor)
6.119 mm (H) x 4.589 mm (V), 7.649 mm Diagonal (Still Mode)
6.413 mm (H) x 3.607 mm (V), 7.358 mm Diagonal (Video Mode)
3856 (H) x 2764 (V) (Entire Sensor)
3664 (H) x 2748 (V) (4:3, Still Mode)
3840 (H) x 2160 (V) (16:9, Video Mode)
1.67 x 1.67
μm
0°, 13.4°
RGB Bayer Pattern
Electronic Rolling Shutter (ERS) with Global Reset Release (GRR)
96 Mp/s
60 MHz
6–48 MHz
Parallel
HiSPi (4-lane)
Frame Rate
Still Mode, 4:3 (3664 (H) x 2748 (V)
Preview Mode
VGA
1080p Mode
(1920 H x 1080 V)
ADC Resolution
Responsivity
Dynamic Range
SNR
MAX
Supply Voltage
I/O Digital
Digital
Analog
SLVS I/O
Power Consumption
Still Mode at 15 fps w/ Serial I/F
Still Mode at 7.5 fps w/ Parallel I/F
Preview
Standby
Power Consumption
Package
Operating Temperature
80 Mp/s at 80 MHz PIXCLK
2.8 Gbps
Programmable up to 15 fps Serial I/F, 7.5 fps Parallel I/F
30 fps with Binning
60 fps with Skip2bin2
60 fps Using HiSPi I/F
30 fps Using Parallel I/F
12-bit, On-die
0.31 V/lux-sec (550 nm)
65.2 dB
34 dB
1.7–1.9 (V) (1.8 (V) Nominal)
or 2.4–3.1 (V) (2.8 (V) Nominal)
1.7–1.9 (V) (1.8 (V) Nominal)
2.4–3.1 (V) (2.8 (V) Nominal)
0.4−0.8 (V) (0.4 or 0.8 (V) Nominal)
638 mW
388 mW
250 mW Low Power VGA
500
μW
(Typical, EXTCLK Disabled)
TBD
48-pin iLCC (10 mm x 10 mm) Bare Die,
48pin Tiny PLCC (12 mm x 12 mm)
−30°C
to +70°C (at Junction)
Value
Active Pixels
Pixel Size
Chief Ray Angle
Color Filter Array
Shutter Type
Maximum Data Rate
Maximum Master Clock
Input Clock Frequency
Maximum Data Rate
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MT9J003
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number
MT9J003D00STMUC2CBC1-200
MT9J003I12STCU-DP
MT9J003I12STCU-DR
MT9J003I12STCV2-DP
MT9J003I12STCV2-TP
MT9J003I12STMU-DP
Product Description
10 MP 1” CIS
10 MP 1/2.3” CIS
10 MP 1/2.3” CIS
10 MP 1/2.3” CIS
10 MP 1/2.3” CIS
10 MP 1/2.3” CIS
Orderable Product Attribute Description
†
Die Sales, 200
μm
Thickness
Dry Pack with Protective Film
Dry Pack without Protective Film
Dry Pack with Protective Film
Tape & Reel with Protective Film
Dry Pack with Protective Film
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
FUNCTIONAL OVERVIEW
The MT9J003 is a progressive-scan sensor that generates
a stream of pixel data at a constant frame rate. It uses an
on-chip, phase-locked loop (PLL) to generate all internal
clocks from a single master input clock running between
Active−Pixel
Sensor (APS)
Array
6 and 48 MHz. The maximum output pixel rate is 80 Mp/s,
corresponding to a pixel clock rate of 80 MHz. A block
diagram of the sensor is shown in Figure 1.
Timing Control
Sync
Signals
Analog Processing
ADC
Shading
Correction
Scaler
Limiter
FIFO
Data
Out
Control Registers
Two-wire
Serial
Interface
Figure 1. Block Diagram
The core of the sensor is a 10 Mp active-pixel array. The
timing and control circuitry sequences through the rows of
the array, resetting and then reading each row in turn. In the
time interval between resetting a row and reading that row,
the pixels in the row integrate incident light. The exposure
is controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the
columns is sequenced through an analog signal chain
(providing offset correction and gain), and then through an
ADC. The output from the ADC is a 12-bit value for each
pixel in the array. The ADC output passes through a digital
processing signal chain (which provides further data path
corrections and applies digital gain).
The pixel array contains optically active and
light-shielded (“dark”) pixels. The dark pixels are used to
provide data for on-chip offset-correction algorithms
(“black level” control).
The sensor contains a set of control and status registers
that can be used to control many aspects of the sensor
behavior including the frame size, exposure, and gain
setting. These registers can be accessed through a two-wire
serial interface.
The output from the sensor is a Bayer pattern; alternate
rows are a sequence of either green and red pixels or blue and
green pixels. The offset and gain stages of the analog signal
chain provide per-color control of the pixel data.
The control registers, timing and control, and digital
processing functions shown in Figure 1 are partitioned into
three logical parts:
•
A sensor core that provides array control and data path
corrections. The output of the sensor core is a 12-bit
parallel pixel data stream qualified by an output data
clock (PIXCLK), together with LINE_VALID (LV) and
FRAME_VALID (FV) signals or a 4-lane serial
high-speed pixel interface (HiSPi).
•
A digital shading correction block to compensate for
color/brightness shading introduced by the lens or chief
ray angle (CRA) curve mismatch.
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3
MT9J003
•
Additional functionality is provided. This includes a
horizontal and vertical image scaler, a limiter, a data
compressor, an output FIFO, and a serializer.
exposure time. Additional I/O signals support the provision
of an external mechanical shutter.
Pixel Array
The output FIFO is present to prevent data bursts by
keeping the data rate continuous. Programmable slew rates
are also available to reduce the effect of electromagnetic
interference from the output interface.
A flash output signal is provided to allow an external
xenon or LED light source to synchronize with the sensor
The sensor core uses a Bayer color pattern, as shown in
Figure 2. The even-numbered rows contain green and red
pixels; odd-numbered rows contain blue and green pixels.
Even-numbered columns contain green and blue pixels;
odd-numbered columns contain red and green pixels.
Column Readout Direction
.
.
.
Black Pixels
First Clear
Active Pixel
(100, 69)
Row
Readout
Direction
B
G2
B
G2
B
...
G1
R
G1
R
G1
B
G2
B
G2
B
G1
R
G1
R
G1
Figure 2. Block Diagram
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MT9J003
OPERATING MODES
By default, the MT9J003 powers up with the serial pixel
data interface enabled. The sensor can operate in serial
HiSPi or parallel mode
For low-noise operation, the MT9J003 requires separate
power supplies for analog and digital power. Incoming
digital and analog ground conductors should be placed in
such a way that coupling between the two are minimized.
Both power supply rails should also be routed in such a way
that noise coupling between the two supplies and ground is
minimized.
CAUTION:
ON Semiconductor does not recommend the
use of inductance filters on the power
supplies or output signals.
HiSPi
Analog Analog
PHY I/O PLL
1
Power
1
Power
1
Power
1
Power
Digital
Digital I/0 Core
Power
1
Power
1
1.5 kW
2, 3
V
DD
_SLVS
1.5 kW
2
V
DD
_SLVS_TX
V
DD
_IO V
DD
V
DD
_PLL V
AA
VAA_PIX
SLVS_0P
SLVS_0N
SLVS_1P
SLVS_1N
SLVS_2P
SLVS_2N
SLVS_3P
SLVS_3N
SLVSC_P
SLVSC_N
SHUTTER
FLASH
To
Controller
Master clock
(6–48 MHz)
EXTCLK
From
Controller
S
DATA
SCLK
GPI[3:0]
4
RESET_BAR
TEST
GND_PLL D
GND
PIXGND
A
GND
V
DD
_IO
V
DD
V
DD
_SLVS_TX V
DD
_PLL
V
AA
VAA_PIX
Digital
ground
Analog
ground
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
All power supplies should be adequately decoupled.
ON Semiconductor recommends a resistor value of 1.5 kΩ, but it may be greater for slower two-wire speed.
This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.
The GPI pins can be statically pulled HIGH or LOW to be used as module IDs, or they can be programmed to perform
special functions (TRIGGER, OE_N, S
ADDR
, STANDBY) to be dynamically controlled.
V
PP
, which can be used during the module manufacturing process, is not shown in Figure 3. This pad is left unconnected
during normal operation.
The parallel interface output pads can be left unconnected if the serial output interface is used.
ON Semiconductor recommends that 0.1
μ
F and 10
μF
decoupling capacitors for each power supply are mounted as
close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Check
the MT9J003 demo headboard schematics for circuit recommendations
ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital
power planes is minimized.
The signal path between the HiSPi serial transmitter and receiver should be adequately designed to minimize any
trans-impedance mismatch and/or reflections on the data path.
Figure 3. Typical Configuration: Serial Four-Lane HiSPi Interface
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