divided into two groups each serving 12 logic cells. Each
group shares half (60) of the 120 product-terms available.
The PA7572’s logic and I/O cells (LCCs, IOCs) are
extremely flexible with up to three output functions per cell
(a total of 72 for all 24 logic cells). Cells are configurable as
D, T, and JK registers with independent or global clocks,
resets, presets, clock polarity, and other features, making
the PA7572 suitable for a variety of combinatorial,
synchronous and asynchronous logic applications. The
PA7572 supports speeds as fast as 13ns/20ns (tpdi/tpdx)
and 66.6MHz (f
MAX
) at moderate power consumption
140mA (100mA typical). Packaging includes 40-pin DIP
and 44-pin PLCC (see Figure 1). Anachip and popular
third-party development tool manufacturers provide
development and programming support for the PA7572.
Figure 1. Pin Configuration
DIP (600 mil)
I/CLK1
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
G ND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I/CLK2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G ND
I/O
I
I
I
I/CLK1
VCC
VCC
I
I
I
I/O
Figure 2. Block Diagram
2 Input/
G lobal Clock Pins
G ND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6 5 4 3 2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
PLCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G ND
7
8
9
10
11
12
13
14
15
16
17
G lobal
Ce lls
12 Input Pins
Input
Cells
(INC)
2
124 (62X2)
Array Inputs
true and
com plem ent
24
Buried
logic
Logic
func tions
to I/O cells
I/O
Cells
(IO C)
24 I/O Pins
12
I/CLK
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
Global C ells
VCC
I
I/O Cells
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I/CLK 2
24
Lo gic
A rray
I/O
I
I
I
I/CLK1
VCC
VCC
I
I
I/O
I
I
I/O
I
I
G ND
G ND
I/CLK2
I
I
I
I/O
Input Cells
A
B
C
D
Logic
Control
Cells
(LCC)
24
24
T Q FP
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
I/O
I
I
I
G ND
G ND
I/CLK2
I
I
I
I/O
G ND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4 sum term s
5 product term s
for G lobal Cells
96 sum term s
(four per LCC)
24 Logic Control Cells
up to 3 output functions per cell
(72 total output functions
possible)
Logic C ontrol Cells
08-15-001A
GND
PA7572
08-15-002A
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights
under any patent accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/10
Inside the Logic Array
The heart of the PEEL™ Array architecture is based on a
logic array structure similar to that of a PLA (programmable
AND, programmable OR). The logic array implements all
logic functions and provides interconnection and control of
the cells. In the PA7572 PEEL™ Array, 62 inputs are
available into the array from the I/O cells, inputs cells and
input/global-clock pins.
All inputs provide both true and complement signals, which
can be programmed to any product term in the array. The
PA7572 PEEL™ Arrays contains 124 product terms. All
product terms (with the exception of certain ones fed to the
global cells) can be programmably connected to any of the
sum-terms of the logic control cells (four sum-terms per
logic control cell). Product-terms and sum-terms are also
routed to the global cells for control purposes. Figure 3
shows a detailed view of the logic array structure.
products functions provided to the logic cells can be used for
clocks, resets, presets and output enables instead of just
simple product-term control.
The PEEL™ logic array can also implement logic functions
with many product terms within a single-level delay. For
example a 16-bit comparator needs 32 shared product terms
to implement 16 exclusive-OR functions. The PEEL™ logic
array easily handles this in a single level delay. Other
PLDs/CPLDs either run out of product-terms or require
expanders or additional logic levels that often slow
performance and skew timing.
Logic Control Cell (LCC)
Logic Control Cells (LCC) are used to allocate and control the
logic functions created in the logic array. Each LCC has four
primary inputs and three outputs. The inputs to each LCC are
complete sum-of-product logic functions from the array, which
can be used to implement combinatorial and sequential logic
functions, and to control LCC registers and I/O cell output
enables.
From G lobal Cell
From
IO Cells
(IO C,INC,
I/CLK)
62 Array Inputs
System Clock
Preset
RegT ype Reset
On/Off
M UX
P
D,T,J
Q
To
Array
From
Logic
Control
Cells
(LCC)
M UX
K
REG
R
From
Array
To
G lobal
Cells
125 Product
Term s
A
B
C
D
M UX
To
I/O
Cell
To
Logic Control
Cells
(LCC)
08-15-004A
Figure 4. Logic Control Cell Block Diagram
As shown in Figure 4, the LCC is made up of three signal
routing multiplexers and a versatile register with synchronous
or asynchronous D, T, or JK registers (clocked-SR registers,
which are a subset of JK, are also possible). See Figure 5.
EEPROM memory cells are used for programming the
desired configuration. Four sum-of-product logic functions
(SUM terms A, B, C and D) are fed into each LCC from the
logic array. Each SUM term can be selectively used for
multiple functions as listed below.
08-15-003A
PA7572 Logic Array
100 Sum Term s
Figure 3. PA7572 Logic Array
True Product-Term Sharing
The PEEL™ logic array provides several advantages over
common PLD logic arrays. First, it allows for true product-
term sharing, not simply product-term steering, as com-
monly found in other CPLDs. Product term sharing ensures
that product-terms are used where they are needed and
not left unutilized or duplicated. Secondly, the sum-of-
Anachip Corp.
www.anachip.com.tw
2/10
Rev. 1.0 Dec 16, 2004
Sum-A = D, T, J or Sum-A
Sum-B = Preset, K or Sum-B
Sum-C = Reset, Clock, Sum-C
Sum-D = Clock, Output Enable, Sum-D
D
P
D Register
Q = D after clocked
Q
Best for storage, sim ple counters,
shifters and state m achines w ith
few hold (loop) conditions.
Sum A, B or C combinatorial paths. Thus, one LCC output
can be registered, one combinatorial and the third, an output
enable, or an additional buried logic function. The multi-
function PEEL™ Array logic cells are equivalent to two or
three macrocells of other PLDs, which have one output per
cell. They also allow registers to be truly buried from I/O pins
without limiting them to input-only (see Figure 8 & Figure 9).
From G lobal Cell
Input Cell Clock
R
T
P
Q
T Register
Q toggles w hen T = 1
Q holds w hen T = 0
Best for w ide binary counters (saves
product term s) and state m achines
w ith m any hold (loop) conditions.
R
REG/
Latch
Q
J
K
P
Q
JK Register
Q toggles w hen J/K = 1/1
Q holds w hen J/K = 0/0
Q= 1
w hen J/K = 1/0
Q= 0
w hen J/K = 0/1
Com bines features of both D and T
registers.
08-15-005A
Input
M UX
Input
To
Array
Input Cell (INC)
R
From G lobal Cell
Input Cell Clock
Figure 5. LCC Register Types
SUM-A can serve as the D, T, or J input of the register or a
combinatorial path. SUM-B can serve as the K input, or the
preset to the register, or a combinatorial path. SUM-C can
be the clock, the reset to the register, or a combinatorial
path. SUM-D can be the clock to the register, the output
enable for the connected I/O cell, or an internal feedback
node. Note that the sums controlling clocks, resets, presets
and output enables are complete sum-of-product functions,
not just product terms as with most other PLDs. This also
means that any input or I/O pin can be used as a clock or
other control function.
Several signals from the global cell are provided primarily
for synchronous (global) register control. The global cell
signals are routed to all LCCs. These signals include a
high-speed clock of positive or negative polarity, global
preset and reset, and a special register-type control that
selectively allows dynamic switching of register type. This
last feature is especially useful for saving product terms
when implementing loadable counters and state machines
by dynamically switching from D-type registers to load and
T-type registers to count (see Figure 9).
Q
RE G/
Latch
To
Array
Input
M UX
M UX
From
Logic
Control
Cell
A,B,C
or
Q
M UX
I/O Pin
M UX
D
1 0
I/O Cell (IO C)
08-15-006A
Figure 6. Input and I/O Cell Block Diagrams
D
Q
IOC/INC Register
Q = D after rising edge of clock
holds until next rising edge
L
Q
Multiple Outputs Per Logic Cell
An important feature of the logic control cell is its capability
to have multiple output functions per cell, each operating
independently. As shown in Figure 4, two of the three
outputs can select the Q output from the register or the
Anachip Corp.
www.anachip.com.tw
3/10
IOC/INC Latch
Q = L w hen clock is high
holds value w hen clock is low
08-15-007A
Figure 7. IOC/INC Register Configurations
Rev. 1.0 Dec 16, 2004
Input Cells (INC)
Input cells (INC) are included on dedicated input pins. The
block diagram of the INC is shown in Figure 6. Each INC
consists of a multiplexer and a register/transparent latch,
which can be clocked from various sources selected by the
global cell (see Figure 7). The register is rising edge
clocked. The latch is transparent when the clock is high
and latched on the clock’s falling edge. The register/ latch
can also be bypassed for a non-registered input.
Global Cells
The global cells, shown in Figure 10, are used to direct global
clock signals and/or control terms to the LCCs, IOCs and
INCs. The global cells allow a clock to be selected from the
CLK1 pin, CLK2 pin, or a product term from the logic array
(PCLK). They also provide polarity control for INC and IOC
clocks enabling rising or falling clock edges for input
registers/latches. Note that each individual LCC clock has its
own polarity control. The global cell for LCCs includes sum-
of-products control terms for global reset and preset, and a
fast product term control for LCC register-type, used to save
product terms for loadable counters and state machines (see
Figure 11). The PA7572 provides two global cells that divide
the LCC and IOCs into groups, A and B. Half of the LCCs and
IOCs use global cell A, half use global cell B. This means that
two high-speed global clocks can be used among the LCCs.
CLK1
CLK2
M UX
PCLK
INC Clocks
I/O Cell (IOC)
All PEEL™ Arrays have I/O cells (IOC) as shown above in
Figure 6. Inputs to the IOCs can be fed from any of the
LCCs in the array. Each IOC consists of routing and control
multiplexers, an input register/transparent latch, a three-
state buffer and an output polarity control. The register/
latch can be clocked from a variety of sources determined
by the global cell. It can also be bypassed for a non-
registered input. The PA7572 allows the use of SUM-D as
a feedback to the array when the I/O pin is a dedicated
output. This allows for additional buried registers and logic
paths. (See Figure 8 and Figure 9).
G lobal Cell: INC
Group A & B
CLK1
CLK2
Q D
M UX
LCC Clocks
M UX
PCLK
IOC Clocks
Input with optional
register/latch
I/O
Reg-Type
Preset
LCC Reg-Type
LCC Presets
LCC Resets
I/O with
independent
output enable
A
B
C
D
D Q
Reset
G lobal Cell: LCC & IO C
08-15-010A
1
2
OE
08-15-008A
Figure 10. Global Cells
Reg-Type from Glob al Cell
Figure 8. LCC & IOC With Two Outputs
D
Q D
Register Ty pe Change Feature
P
Q
Global Cell can dynam ically change user-
selected LCC registers from D to T or from D
to JK. This saves product term s for loadable
counters or state m achines. Use as D register
to load, use as T or JK to count. Tim ing
allow s dynam ic operation.
Buried register or
logic paths
O utput
R
A
B
C
D
D Q
1
T
2
3
P
Example:
Product term s for 10 bit loadable binary counter
Q
D uses 57 product term s (47 count, 10 load)
T uses 30 product term s (10 count, 20 load)
D/T uses 20 product term s (10 count, 10 load)
08-15-011 A
R
08-15-009A
Figure 9. LCC & IOC With Three Outputs
Anachip Corp.
www.anachip.com.tw
4/10
Figure 11. Register Type Change Feature
Rev. 1.0 Dec 16, 2004
PEEL™ Array Development Support
Development support for PEEL™ Arrays is provided by
Anachip and manufacturers of popular development tools.
Anachip offers the powerful PLACE Development Software
(free to qualified PLD designers).
The PLACE software includes an architectural editor, logic
compiler, waveform simulator, documentation utility and a
programmer interface. The PLACE editor graphically
illustrates and controls the PEEL™ Array’s architecture,
making the overall design easy to understand, while
allowing the effectiveness of boolean logic equations, state
machine design and truth table entry. The PLACE compiler
performs logic transformation and reduction, making it
possible to specify equations in almost any fashion and fit
the most logic possible in every design. PLACE also
provides a multi-level logic simulator allowing external and
internal signals to be simulated and analyzed via a
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