19-6029; Rev 0; 9/11
EVALUATION KIT AVAILABLE
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
General Description
The MAX3636 is a highly flexible, precision phase-locked
loop (PLL) clock generator optimized for the next gen-
eration of network equipment that demands low-jitter
clock generation and distribution for robust high-speed
data transmission. The device features subpicosecond
jitter generation, excellent power-supply noise rejection,
and pin-programmable LVDS/LVPECL output interfaces.
The MAX3636 provides nine differential outputs and one
LVCMOS output, divided into three banks. The frequency
and output interface of each output bank can be individu-
ally programmed, making this device an ideal replace-
ment for multiple crystal oscillators and clock distribution
ICs on a system board, saving cost and space.
This 3.3V IC is available in a 7mm x 7mm, 48-pin TQFN
package and operates from -40°C to +85°C.
Features
S Inputs
CrystalInterface:18MHzto33.5MHz
LVCMOSInput:15MHzto160MHz
DifferentialInput:15MHzto350MHz
S Outputs
LVCMOSOutput:Upto160MHz
LVPECL/LVDSOutputs:Upto800MHz
S ThreeIndividualOutputBanks
Pin-ProgrammableDividers
Pin-ProgrammableOutputInterface
S WideVCOTuningRange(3.60GHzto4.025GHz)
S LowPhaseJitter
0.34ps
RMS
(12kHzto20MHz)
0.14ps
RMS
(1.875MHzto20MHz)
S ExcellentPower-SupplyNoiseRejection
S -40NCto+85NCOperatingTemperatureRange
S 3.3VSupply
Ordering Information
appears at end of data sheet.
Applications
Ethernet Switches/
Routers
Wireless Base Stations
SONET/SDH Line Cards
PCIe®, Network
Processors
Fibre Channel SAN
Functional Diagram
LVPECL/LVDS
QA0
QA0
LVPECL/LVDS
QA1
QA1
LVPECL/LVDS
XOUT
XO
XIN
LVCMOS
CIN
PLL, DIVIDERS, MUXES
VCO
LVPECL/LVDS
LVPECL/LVDS
QA2
QA2
QA3
QA3
LVPECL/LVDS
QA4
QA4
QB0
QB0
LVPECL
DIN
DIN
LVPECL/LVDS
LVPECL/LVDS
QB1
QB1
QB2
QB2
LVPECL/LVDS
QC
QC
LVCMOS
QCC
MAX3636
PCIe is a registered trademark of PCI-SIG Corp.
1
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
ABSOLUTEMAXIMUMRATINGS
Supply Voltage Range (V
CC
, V
CCA
, V
CCQA
,
V
CCQB
, V
CCQC
, V
CCQCC
)................................-0.3V to +4.0V
Voltage Range at CIN, IN_SEL, DM, DF[1:0],
DP[1:0], PLL_BP, DA[1:0], DB[1:0], DC[1:0],
QA_CTRL1, QA_CTRL2, QB_CTRL,
QC_CTRL, QCC ................................... -0.3V to (V
CC
+ 0.3V)
Voltage Range at DIN,
DIN
........ (V
CC
- 2.35V) to (V
CC
- 0.35V)
Voltage Range at QA[4:0],
QA[4:0],
QB[2:0],
QB[2:0],
QC,
QC
when LVDS Output .. -0.3V to (V
CC
+ 0.3V)
Current into QA[4:0],
QA[4:0],
QB[2:0],
QB[2:0],
QC,
QC
when LVPECL Output ..................................... -56mA
Current into QCC.............................................................
Q50mA
Voltage Range at XIN ...........................................-0.3V to +1.2V
Voltage Range at XOUT .............................-0.3V to (V
CC
- 0.6V)
Continuous Power Dissipation (T
A
= +70NC)
TQFN (derate 40mW/NC above +70NC).....................3200mW
Operating Junction Temperature Range ......... -55NC to +150NC
Storage Temperature Range............................ -65NC to +160NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICALCHARACTERISTICS
(V
CC
= 3.0V to 3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted. Signal applied to
CIN or DIN/DIN only when selected as the reference clock.) (Notes 1, 2)
PARAMETER
Supply Current with PLL
Enabled (Note 3)
Supply Current with PLL
Bypassed (Note 3)
SYMBOL
I
CC
CONDITIONS
Configured with LVPECL outputs
Configured with LVDS outputs
Configured with LVPECL outputs
Configured with LVDS outputs
MIN
TYP
170
290
110
230
MAX
215
365
UNITS
mA
mA
LVCMOS/LVTTLCONTROLINPUTS(IN½SEL,DM,DF[1:0],DA[1:0],DB[1:0],DC[1:0],PLL½BP,DP[1:0],QA½CTRL1,
QA½CTRL2,QB½CTRL,QC½CTRL)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Reference Clock Input
Frequency
Input Amplitude Range
Input High Current
Input Low Current
Reference Clock Input Duty
Cycle
Input Capacitance
DIFFERENTIALCLOCKINPUT(DIN,DIN)(Note5)
Differential Input Frequency
Input Bias Voltage
Input Differential Voltage Swing
f
REF
V
CMI
15
V
CC
-
1.8
150
V
CC
-
1.3
1800
350
MHz
V
mV
P-P
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
V
IN
= V
CC
V
IN
= 0V
-80
2.0
0.8
80
V
V
FA
FA
LVCMOS/LVTTLCLOCKINPUT(CIN)
f
REF
Internally AC-coupled (Note 4)
V
IN
= V
CC
V
IN
= 0V
15
1.2
-80
40
1.5
60
160
3.6
80
MHz
V
P-P
FA
FA
%
pF
2
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
ELECTRICALCHARACTERISTICS(continued)
(V
CC
= 3.0V to 3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted. Signal applied to
CIN or DIN/DIN only when selected as the reference clock.) (Notes 1, 2)
PARAMETER
Single-Ended Voltage Range
Input Differential Impedance
Differential Input Capacitance
LVDSOUTPUTS(QA[4:0],QA[4:0],QB[2:0],QB[2:0],QC,QC)(Note6)
Output Frequency
Output High Voltage
Output Low Voltage
Differential Output Voltage
Change in Magnitude
of Differential Output for
Complementary States
Output Offset Voltage
Change in Magnitude of
Output Offset Voltage for
Complementary States
Differential Output Impedance
Output Current
Output Current When Disabled
Output Rise/Fall Time
Output Duty-Cycle Distortion
Short together
Short to ground
V
Q__
= V
Q__
= 0V to V
CC
20% to 80%
PLL enabled
PLL bypassed (Note 7)
48
V
OH
V
OL
|V
OD
|
D|V
OD
|
V
OS
D|V
OS
|
78
100
3
6
10
160
50
50
800
V
OH
V
OL
V
CC
-
1.13
V
CC
-
1.85
0.5
V
Q__
= V
Q__
= 0V to V
CC
20% to 80%
PLL enabled
PLL bypassed (Note 7)
48
V
CC
-
0.98
V
CC
-
1.70
0.7
10
140
50
50
240
52.1
V
CC
-
0.83
V
CC
-
1.55
0.9
240
52
1.125
0.925
250
400
25
1.3
25
140
800
1.475
MHz
V
V
mV
mV
V
mV
I
mA
FA
ps
%
SYMBOL
CONDITIONS
MIN
V
CC
-
2.0
80
100
1.5
TYP
MAX
V
CC
-
0.7
120
UNITS
V
I
pF
LVPECLOUTPUTS(QA[4:0],QA[4:0],QB[2:0],QB[2:0],QC,QC)(Note8)
Output Frequency
Output High Voltage
Output Low Voltage
Output-Voltage Swing
(Single-Ended)
Output Current When Disabled
Output Rise/Fall Time
Output Duty-Cycle Distortion
MHz
V
V
V
P-P
FA
ps
%
3
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
ELECTRICALCHARACTERISTICS(continued)
(V
CC
= 3.0V to 3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted. Signal applied to
CIN or DIN/DIN only when selected as the reference clock.) (Notes 1, 2)
PARAMETER
LVCMOS/LVTTLOUTPUT(QCC)
Output Frequency
Output High Voltage
Output Low Voltage
Output Rise/Fall Time
Output Duty-Cycle Distortion
Output Impedance
PLLSPECIFICATIONS
VCO Frequency Range
Phase-Frequency Detector
Compare Frequency
PLL Jitter Transfer Bandwidth
25MHz crystal
input (Note 9)
12kHz to 20MHz
1.875MHz to 20MHz
f
VCO
f
PFD
Low VCO (DP1 = 0 or NC)
High VCO (DP1 = 1)
3600
3830
15
130
0.34
0.14
0.34
-56
-45
6
-70
-111
-113
-119
-136
-147
-115
-116
-122
-139
-149
dBc/
Hz
dBc/
Hz
dBc
dBc
ps
P-P
dBc
1.0
ps
RMS
3750
3932
3830
4025
42
MHz
MHz
kHz
I
OH
= -12mA
I
OL
= 12mA
20% to 80% (Note 9)
PLL enabled
PLL bypassed (Note 7)
150
42
400
50
50
15
2.6
160
V
CC
0.4
850
58
MHz
V
V
ps
%
I
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Integrated Phase Jitter
RJ
25MHz LVCMOS or differential input
(Notes 10, 11)
(Note 12)
(Note 12)
LVPECL or LVDS (Note 12)
(Note 13)
f
OFFSET
= 1kHz
f
OFFSET
= 10kHz
Supply-Noise Induced Phase
Spur at LVPECL/LVDS Output
Supply-Noise Induced Phase
Spur at LVCMOS Output
Determinisitic Jitter Induced by
Power-Supply Noise
Nonharmonic and Subharmonic
Spurs
SSB Phase Noise at 491.52MHz
f
OFFSET
= 100kHz
f
OFFSET
= 1MHz
f
OFFSET
R
10MHz
f
OFFSET
= 1kHz
f
OFFSET
= 10kHz
SSB Phase Noise at 312.5MHz
f
OFFSET
= 100kHz
f
OFFSET
= 1MHz
f
OFFSET
R
10MHz
4
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
ELECTRICALCHARACTERISTICS(continued)
(V
CC
= 3.0V to 3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted. Signal applied to
CIN or DIN/DIN only when selected as the reference clock.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
f
OFFSET
= 1kHz
f
OFFSET
= 10kHz
SSB Phase Noise at 245.76MHz
f
OFFSET
= 100kHz
f
OFFSET
= 1MHz
f
OFFSET
R
10MHz
f
OFFSET
= 1kHz
f
OFFSET
= 10kHz
SSB Phase Noise at 156.25MHz
f
OFFSET
= 100kHz
f
OFFSET
= 1MHz
f
OFFSET
R
10MHz
f
OFFSET
= 1kHz
f
OFFSET
= 10kHz
SSB Phase Noise at 125MHz
f
OFFSET
= 100kHz
f
OFFSET
= 1MHz
f
OFFSET
R
10MHz
f
OFFSET
= 1kHz
f
OFFSET
= 10kHz
SSB Phase Noise at 100MHz
f
OFFSET
= 100kHz
f
OFFSET
= 1MHz
f
OFFSET
R
10MHz
MIN
TYP
-117
-119
-125
-142
-151
-122
-123
-129
-145
-152
-123
-124
-130
-147
-153
-126
-127
-133
-148
-152
dBc/
Hz
dBc/
Hz
dBc/
Hz
dBc/
Hz
MAX
UNITS
Note1:
A series resistor of up to 10.5I is allowed between V
CC
and V
CCA
for filtering supply noise when system power-supply
tolerance is V
CC
= 3.3V
Q5%.
See
Figure 3.
Note2:
Unless otherwise noted, specifications at T
A
= +25NC and T
A
= +85NC are guaranteed by production testing.
Specifications at T
A
= -40NC are guaranteed by design.
Note3:
Measured with all outputs enabled and unloaded.
Note4:
CIN can be AC- or DC-coupled. See
Figure 8.
Input high voltage must be ≤ V
CC
+ 0.3V.
Note5:
DIN can be AC- or DC-coupled. See
Figure 10.
Note6:
Measured with 100I differential load.
Note7:
Measured with crystal input, or with 50% duty cycle LVCMOS or differential input.
Note8:
Measured with output termination of 50I to V
CC
- 2V or Thevenin equivalent.
Note9:
Measured with a series resistor of 33I to a load capacitance of 3.0pF. See
Figure 1.
Note10:
Measured at 156.25MHz.
Note11:
Measured using LVCMOS/LVTTL input with slew rate
R
1.0V/ns, or differential input with slew rate
R
0.5V/ns.
Note12:
Measured at 156.25MHz output with 200kHz, 50mV
P-P
sinusoidal signal on the supply using the crystal input and
the power-supply filter shown in
Figure 3.
See the
Typical Operating Characteristics
for other supply noise frequen-
cies. Deterministic jitter is calculated from the measured power-supply-induced spurs. For more information, refer to
Application Note 4461:
HFAN-04.5.5: Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers.
Note13:
Measured with all outputs enabled and all three banks at different frequencies.
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