CAT6500
3.0 A Power Selector Switch
Description
CAT6500 is an automatic power switch designed to select between
two power sources and direct that power to a load for battery charging
or system power.
CAT6500’s power inputs withstand voltages of up to 18 V and
protect the downstream load from voltages exceeding 7 V. In the event
of a polarity reversal at either input CAT6500’s internal power
switches will shut off to prevent discharge of the system’s internal
power source.
Low resistance power switches handle currents in excess of 3 A and
when OFF block current flow in both directions. CAT6500 can operate
in reverse mode in which internal system power is be directed to either
of the power input ports for powering an external device, such as a
USB On−The−Go appliance.
Features
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WQFN−32
HVA SUFFIX
CASE 485BN
MARKING DIAGRAM
6500
SSSS
ALYW
G
6500
SSSS
A
L
Y
W
G
= Specific Device Code
= Last Four Digits of Assembly Lot Number
= Assembly Location
= Wafer Lot Number (optional)
= Production Year
= Production Week
= Pb−Free Package
•
•
•
•
•
•
•
•
Autonomous Switching between 2 Power Sources
Withstands +18 V to −5 V on Either Power Input
80 mW Switches (typ.) for Low Power Loss
Reverse−Mode for Powering External Devices
Over Voltage Protection of Downstream Load
Compatible with USB−OTG Devices
32−Lead WQFN 4.4 mm x 4.4 mm Package
This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
Typical Applications
•
Mobile Phones
•
PDAs
•
Personal Navigation Devices
PWR_OUT
PS1
SW1_STAT
PS2
CAT6500
VCC
0.1
mF
C1
RM_EN1
RM_EN2
PRIORITY
SW2_STAT
Power Management IC
or Battery Charge
+
−
Li−Ion
ORDERING INFORMATION
Device
CAT6500HVA−T2
Package
WQFN−32
(Pb−Free)
Shipping
†
2,000/
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Figure 1. Typical Application Circuit
©
Semiconductor Components Industries, LLC, 2015
1
November, 2015 − Rev. 2
Publication Order Number:
CAT6500/D
CAT6500
PS1 Detect
OVP Detect
−
150 mV
PS1
PWR_OUT
+
−
+
−
+
SW1
PWR_OUT
1.7 V
7V
Level
Shifter
SW1_STAT
VCC
C1
Voltage
Source
Selection
PRIORITY
V Ref
Thermal
Shutdown
Charge
Pump
Level
Shifter
1.7 V
7V
SW2
Control
Logic
RM_EN1
RM_EN2
SW2_STAT
150 mV
PS2
−
+
−
+
−
+
PS2 Detect
OVP Detect
GND
Figure 2. Simplified Block Diagram
PIN CONNECTIONS
PWR_OUT
PWR_OUT
PWR_OUT
PS1
PS1
PS1
32
1
PWR_OUT
PWR_OUT
PWR_OUT
PWR_OUT
NIC
PS2
PS2
PS2
PS2
33
34
PWR_OUT
35
GND or
Floating
36
PS1
SW1_STAT
SW2_STAT
PS1
RM_EN1
GND
RM_EN2
PRIORITY
NIC
PS2
PS2
NIC
NIC
C1
VCC
(Top View)
Figure 3. Pin Connections w/Rear Pads Shown
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2
GND
NIC
PS1
NIC
CAT6500
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
1, 2, 3, 4
5
6, 7, 8, 9, 10
11, 12
13
14
15
16
17
18
19
20
21
22
23
24
25, 26, 27, 28
29
30, 31, 32
33
34
35
Pin Name
PWR_OUT
NIC
PS2
NIC
VCC
GND
C1
NIC
NIC
PRIORITY
RM_EN2
GND
RM_EN1
PS1
SW2_STAT
SW1_STAT
PS1
NIC
PWR_OUT
PWR_OUT
PS2
–
Description
Power Output. Must be tied to PWR_OUT on opposite side of chip. Use all 3 pins each side.
No Internal Connection. A signal or voltage applied to this pin will have no effect on device operation.
Power Source #2. External power input
No Internal Connection. A signal or voltage applied to this pin will have no effect on device operation.
Power input from battery.
Ground. Reference point for all voltages.
Filter capacitor for CAT6500’s internal power bus
No Internal Connection. A signal or voltage applied to this pin will have no effect on device operation.
No Internal Connection. A signal or voltage applied to this pin will have no effect on device operation.
Priority selects preferred power source when both PS1 and PS2 are powered.
Reverse Mode Enable 2. Overrides PRIORITY and turns SW2 ON.
Ground. Reference point for all voltages.
Reverse Mode Enable 1. Overrides PRIORITY and turns SW1 ON.
Power Source #1. External power input.
Power Source 2 Status. An open drain LOW true logic level output indicating that the switch SW2 is
turned on.
Power Source 1 Status. An open drain LOW true logic level output indicating that the switch SW1 is
turned on.
Power Source #1. External power input.
No Internal Connection. A signal or voltage applied to this pin will have no effect on device operation.
Power Output. Must be tied to PWR_OUT on opposite side of chip. Use all 3 pins each side.
Electrically active thermal pad. Does not need to be connected to other PWR_OUTs. Can be left float-
ing but must not be connected to other signal paths or Ground.
Electrically active thermal pad. Does not need to be connected to other PS2 pins. Can be left floating
but must not be connected to other signal paths or Ground.
Mechanical support for control IC. This chip does not generate any significant heat and does not need
a separate heat sinking connection. Electrically this may be left floating or can be grounded. It should
NOT be connected to other signals or voltages.
Electrically active thermal pad. Does not need to be connected to other PS1 pins. Can be left floating
but must not be connected to other signal paths or Ground.
36
PS1
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CAT6500
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Input Voltage Range (Note 1)
Symbol
V
PS
V
CC
,
V
PWR_OUT
Control Logic Input Range
Control Logic Output Range
Maximum Junction Temperature
Storage Temperature Range
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
V
L_IN
V
L_OUT
T
J(max)
T
STG
ESD
HBM
ESD
MM
T
SLD
Pin
PS1, PS2
VCC, C1, PWR_OUT
RM_ENx, PRIORITY
SW1_STAT, SW2_STAT
–
–
ALL
ALL
ALL
Range
−5.0 to 18
−0.3 to 6.0
−0.3 to 6.0
−0.3 to 6.0
150
−65 to 150
2
200
260
V
V
°C
°C
kV
V
°C
Unit
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating:
≤
150 mA per JEDEC standard: JESD78
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 3. THERMAL CHARACTERISTICS
(Note 4)
Parameter
Thermal Characteristics, TDFN−32 4.4 x 4.4 mm
Thermal Resistance, Junction−to−Air, 1 sq. Inch, 1 oz. Copper Clad PCB
Thermal Resistance, Junction−to−Air, 1 sq. Inch, 2 oz. Copper Clad PCB
Symbol
R
θJA
59
54
Value
Unit
°C/W
4. Values based on copper area of 645 mm
2
(or 1 in
2
) of 1 oz copper thickness and FR4 PCB substrate.
Table 4. RECOMMENDED OPERATING CONDITIONS
Parameter
Input Voltage PS1, PS2
Symbol
V
CC
V
PWR_OUT
V
PS1
, V
PS2
Output Current
Control Logic; Inputs and Outputs
Ambient Temperature
I
PWR_OUT
V
L_IN
, V
L_OUT
T
A
Min
1.6
0
−5
0
0
−40
Max
5.5
5.5
7.7
3.3
5.5
+85
A
V
°C
Unit
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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CAT6500
Table 5. ELECTRICAL OPERATING CHARACTERISTICS
Parameter
INPUT / OUTPUT
Input Voltage
PS1 or PS2 normal operation mode
PS1 or PS2 overvoltage protection mode
VCC
Operating Current; SW1 and SW2 ON
Measured at VCC
RM_EN1 = 1, RM_EN2 = 1
1.7 V < PS1 < 2.4 V, 1.7 V < PS2 < 2.4 V
Measured at VCC
PRIORITY = 1, RM_EN1 = 0, RM_EN2 = 0
PS1 < 1.5 V, PS2 < 1.5 V
PS1, PS2, voltage rising
PS1, PS2, voltage falling
Over Voltage Detection
Over Voltage Hysteresis
Reverse Voltage Detect Threshold
POWER SWITCHES
Switch Resistance; SW1, SW2
Measured from PSx to PWR_OUT
PS1 or PS2 = 2.5 V, 5°C
PS1 or PS2 = 5 V, 25°C
PS1 or PS2 = 5 V, −40°C to +85°C
LOGIC
Input Threshold Voltage
Voltage Increasing, Logic High
PRIORITY, RM_EN1, RM_EN2
Voltage Decreasing, Logic Low
PRIORITY, RM_EN1, RM_EN2
Input Current
PRIORITY, Pull−Up
RM_ENx, Pull−Down
Output Current HIGH
Output Voltage LOW
TIMING
SW Turn−on Delay Time
SW Rise Time
Measured from rising edge of RM_ENx
to 10% of voltage at PSx; PSx = 2.0 V
Measured at PWR_OUT
10% to 90% of voltage applied at PSx
PS = 2.0 V
Measured at PWR_OUT
10% to 90% of voltage applied at PSx
PS = 5 V
SW Turn−off Time
Over Voltage Turn−off Time
Measured at PWR_OUT
90% to 10% of voltage applied at PSx
PS = 0 V
³
10 V
PS = 5 V
³
10 V
Break−Before−Make Off Time
THERMAL SHUTDOWN
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
T
SD
T
SH
–
–
145
10
–
–
°C
°C
Measured at PWR_OUT, OFF time during
transition from PS1
³
PS2 or PS2
³
PS1
t
OFF
t
OFF_OV1
t
OFF_OV2
t
OFF_BBM
t
ON_DLY
t
RISE
−
−
100
200
−
300
ms
ms
V
OH
= V
IN
– 0.3 V
SW1_STAT, SW2_STAT
I
OL
= 3.0 mA
SW1_STAT, SW2_STAT
I
OH
V
OL
V
th_HIGH
V
th_LOW
I
IN
1.0
0.4
−
−
−
−
−
−
10
10
10
0.3
1.5
0.8
20
20
15
0.4
mA
V
mA
V
R
ON
−
−
−
80
−
−
110
−
135
mW
PS1, PS2, voltage rising
PS1, PS2, voltage falling
PS1, PS2
V
PS
V
PS
V
CC
I
VCC
1.6
1.6
2.5
−
3.9
3.9
3.9
85
7.7
12
5.5
120
mA
V
(V
CC
= 3.9 V, C1 = 0.1
mF,
unless otherwise noted. Typical values T
A
= 25°C, Min/Max values T
A
= −40°C to +85°C.)
Test Conditions
Symbol
Min
Typ
Max
Unit
Quiescent Current; SW1 and SW2 OFF
I
VCC
−
35
45
mA
Input Voltage Detect
V
DETR
V
DETF
V
OVP
V
HYS
V
REV
1.6
0.1
6.5
100
−0.7
1.7
0.15
7.0
−
–
1.8
0.3
7.8
250
−1.0
V
V
mV
V
−
100
250
−
−
−
−
−
10
10
400
25
−
−
−
ms
ms
ms
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