19-2577; Rev 2; 5/07
KIT
ATION
EVALU
E
BL
AVAILA
Low-Power, Compact 2.5Gbps/2.7Gbps
Clock-Recovery and Data-Retiming IC
General Description
The MAX3873A is a compact, low-power 2.488Gbps/
2.67Gbps clock-recovery and data-retiming IC for
SDH/SONET applications. The phase-locked loop (PLL)
recovers a synchronous clock signal from the serial NRZ
data input. The input data is then retimed by this recov-
ered clock, providing a clean data output. The MAX3873A
meets all SDH/SONET jitter specifications, does not
require an external reference clock to aid in frequency
acquisition, and provides excellent tolerance to both
deterministic and sinusoidal jitter. The MAX3873A pro-
vides a PLL loss-of-lock (LOL) output to indicate whether
the CDR is in lock. The recovered data and clock outputs
are CML with on-chip 50Ω back terminations on each line.
The clock output can be powered down if not used.
The MAX3873A is implemented in Maxim’s second-gener-
ation SiGe process and consumes only 260mW at 3.3V
supply (output clock disabled, low output swing). The
device is available in a 4mm x 4mm 20-pin QFN
exposed-pad package and operates from -40°C to +85°C.
Features
♦
Fully Integrated Clock Recovery and Data
Retiming
♦
Power Dissipation: 260mW with +3.3V Supply
♦
Clock Jitter Generation: 5mUI
RMS
♦
Exceeds ANSI, ITU, and Bellcore SDH/SONET
Jitter Specifications
♦
Differential Input Range: 50mV
P-P
to 1.6V
P-P
♦
Single +3.3V Power Supply
♦
PLL Fast Track (FASTRACK) Mode Available
♦
Clock Output Can Be Disabled
♦
Input Data Rate: 2.488Gbps or 2.67Gbps
♦
Selectable Output Amplitude
♦
Tolerates 2000 Consecutive Identical Digits
♦
Loss-of-Lock Indicator
♦
Differential CML Data and Clock Outputs
♦
Operating Temperature Range: -40°C to +85°C
MAX3873A
Applications
Switch Matrix Backplanes
SDH/SONET Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
SDH/SONET Test Equipment
DWDM Transmission Systems
PART
MAX3873AEGP
MAX3873AETP+
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
20 QFN
(4mm x 4mm)
20 TQFN
(4mm x 4mm)
PKG
CODE
G2044-3
T2044-3
Pin Configuration
GND
FIL+
GND
LOL
FIL-
+
Denotes lead-free package.
TOP VIEW
20
19
18
17
RATESET
V
CC
SDI+
SDI-
V
CC
1
2
3
4
5
10
16
15
14
13
SDO+
SDO-
VCC_BUF
SCLKO+
SCLKO-
Typical Application Circuit appears at end of data sheet.
MAX3873A
12
11
6
7
8
FASTRACK
MODE
9
QFN/TQFN**
**NOTE: THE EXPOSED PAD MUST BE
SOLDERED TO THE SUPPLY GROUND.
________________________________________________________________
Maxim Integrated Products
VCC_VCO
SCLKEN
V
CC
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
MAX3873A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
..............................................-0.5V to +5.0V
Voltage at SDI± .............................. (V
CC
- 1.0V) to (V
CC
+ 0.5V)
CML Output Current at SDO±, SCLKO± ............................22mA
Voltage at
LOL,
FASTRACK, FIL±, SCLKEN
MODE, RATESET...................................-0.5V to (V
CC
+ 0.5V)
Continuous Power Dissipation (T
A
= +85°C)
20-Lead QFN (derate 20.0mW/°C above +85°C) .....1300mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-50°C to +150°C
Processing Temperature..................................................+400°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0V to 3.6V, T
A
= -40°C to +85°C. Typical values are at 2.488Gbps, V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Supply Current (Note 2)
SYMBOL
I
CC
CONDITIONS
MODE = GND, SCLKEN = low
MODE = OPEN, SCLKEN = high
Figure 1
Figure 1
DC-coupled, Figure 1
R
IN
MODE = open
Differential Output Swing
(Note 3)
Differential Output
Resistance
Output Common-Mode
Voltage (Note 3)
MODE = V
CC
MODE = GND
R
O
MODE = Open
MODE = V
CC
MODE = GND
TTL INPUT/OUTPUT SPECIFICATIONS (FASTRACK, LOL, SCLKEN, MODE, RATESET)
Input High Voltage
Input Low Voltage
Input Current
Output High Voltage
Output Low Voltage
V
OH
V
OL
I
OH
= sourcing 40µA
I
OL
= sinking 2mA
V
IH
V
IL
-30
2.4
0.4
2.0
0.8
+30
V
V
µA
V
V
50
V
CC
- 0.8
V
CC
- V
ID
/4
40
640
400
200
80
50
800
600
400
100
V
CC
- 0.17
V
CC
- 0.13
V
CC
- 0.08
V
60
1000
800
600
120
Ω
mV
P-P
MIN
TYP
79
112
MAX
99
142
1600
V
CC
+ 0.4
UNITS
mA
CML INPUT SPECIFICATIONS (SDI+, SDI-)
Differential Input Voltage
Single-Ended Input
Voltage
Input Common-Mode
Voltage
Input Termination to V
CC
V
ID
V
IS
mV
P-P
V
V
Ω
CML OUTPUT SPECIFICATIONS (SDO+, SDO-, SCLKO+, SCLKO-)
2
_______________________________________________________________________________________
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0V to 3.6V, C
F
= 0.022µF, T
A
= -40°C to +85°C. Typical values are at V
CC
= 3.3V, 2.488Gbps, T
A
= +25°C, unless otherwise
noted.) (Note 4)
PARAMETER
Serial Input Data Rate
Clock-to-Q Delay
Jitter Peaking
Jitter Transfer Bandwidth
t
CLK-Q
J
P
J
BW
SYMBOL
RATESET = low
RATESET = high
Figure 2 (Note 5)
f
≤
2MHz
RATESET = Low
f = 70kHz, 0.4UI deterministic jitter
on input data
f = 100kHz, 0.4UI deterministic jitter
on input data
(Notes 6, 8)
f = 1MHz, 0.4UI deterministic jitter
on input data
f = 10MHz, 0.4UI deterministic jitter
on input data
Sinusoidal Jitter Tolerance
f = 70kHz, 0.4UI deterministic jitter
on input data
f = 100kHz, 0.4UI deterministic jitter
on input data
(Notes 6, 9)
f = 1MHz, 0.4UI deterministic jitter
on input data
f = 10MHz, 0.37UI deterministic jitter
on input data
(Notes 7, 8)
Jitter Generation
J
GEN
(Notes 7, 9)
Clock Output Edge
Speed
Data Output Edge
Speed
Tolerated Consecutive
Identical Digits
SDI± Input Return Loss
(-20log(⏐S
11
⏐))
Frequency Acquisition
Time
LOL
Assert Time
100kHz to 2.5GHz
2.5GHz to 4.0GHz
Figure 4
Figure 4
20% to 80%
20% to 80%
0.33
0.15
0.6
0.3
5
45
6
40
60
60
2000
17
14
1
1.6
6.8
62
7.65
86
110
110
mUI
RMS
mUI
P-P
mUI
RMS
mUI
P-P
ps
ps
bits
dB
ms
µs
2.12
6.9
4.5
0.33
0.15
0.6
0.3
UI
P-P
2.12
6.9
4.5
-70
CONDITIONS
MIN
TYP
2.488
2.67
+70
0.1
2.0
MAX
UNITS
Gbps
ps
dB
MHz
MAX3873A
_______________________________________________________________________________________
3
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
MAX3873A
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.0V to 3.6V, C
F
= 0.022µF, T
A
= -40°C to +85°C. Typical values are at V
CC
= 3.3V, 2.488Gbps, T
A
= +25°C, unless otherwise
noted.) (Note 4)
Note 1:
At T
A
= -40°C, DC characteristics are guaranteed by design and characterization.
Note 2:
CML outputs open.
Note 3:
R
L
= 50Ω to V
CC
.
Note 4:
AC characteristics are guaranteed by design and characterization.
Note 5:
Relative to the falling edge of SCLKO+. See Figure 2.
Note 6:
Measured with 2
23
- 1 PRBS.
Note 7:
Jitter BW = 12kHz to 20MHz.
Note 8:
RATESET = low.
Note 9:
RATESET = high.
V
CC
+ 0.4V
800mV
V
CC
SCLKO+
V
CC
- 0.4V
V
CC
800mV
V
CC
- 0.4V
SDO
(a) AC-COUPLED SINGLE-ENDED INPUT (CML OR PECL)
25mV
t
CLK-Q
25mV
t
CLK
V
CC
- 0.8V
Figure 2. Definition of Clock-to-Q Delay
(b) DC-COUPLED SINGLE-ENDED CML INPUT
Figure 1. Definition of Input Voltage Swing
SERIAL DATA
<2μs
1200 BITS OF 1–0 PATTERN
DATA
VCO CLOCK PHASE ALIGNED TO INPUT DATA
FASTRACK
Figure 3. Definition of Phase Acquisition Time
INPUT DATA
LOL ASSERT TIME
LOL OUTPUT
FREQUENCY ACQUISITION TIME
Figure 4. Definition of
LOL
Assert Time and Frequency Acquisition Time
4
_______________________________________________________________________________________
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
RECOVERED CLOCK AND DATA
(2.488Gbps, 2
23
- 1 PATTERN,
V
IN
= 50mV
P-P
)
MAX3873A toc01
MAX3873A
RECOVERED CLOCK AND DATA
(2.67Gbps, 2
23
- 1 PATTERN,
V
IN
= 50mV
P-P
)
MAX3873A toc02
125mV/div
125mV/div
100ps/div
100ps/div
RECOVERED CLOCK JITTER
(2.488Gbps)
MAX3873A toc03
JITTER TOLERANCE
(2.488Gbps, 2
23
- 1 PATTERN,
V
IN
= 50mV
P-P
)
MAX3873A toc04
100
WITH 0.2UI OF PWD
INPUT JITTER (UIp-p)
10
WITH 0.4UI OF
DETERMINISTIC
JITTER
1
BELLCORE
MASK
0.1
10
100
1000
10,000
2
23
- 1 PATTERN
RMS = 2.0ps
RMS
10ps/div
JITTER FREQUENCY (kHz)
JITTER TRANSFER
MAX3873A toc05
SUPPLY CURRENT vs. TEMPERATURE
(SCLKO DISABLED)
MAX3873A toc06
SUPPLY CURRENT vs. TEMPERATURE
(SCLKO ENABLED)
180
160
SUPPLY CURRENT (mA)
140
120
100
80
60
40
20
0
MIN OUTPUT SWING
MAX OUTPUT SWING
MED OUTPUT SWING
MAX3873A toc07
0.5
0
-0.5
TRANSFER (dB)
-1.0
-1.5
-2.0
-2.5
-3.0
10
3
10
4
10
5
FREQUENCY (Hz)
10
6
200
180
160
SUPPLY CURRENT (mA)
140
120
100
80
60
40
20
MIN OUTPUT SWING
MED OUTPUT SWING
MAX OUTPUT SWING
200
BELLCORE
MASK
10
7
0
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
_______________________________________________________________________________________
5
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