Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on
TA0103A
Stereo 250W (4Ω) Class-T Digital Audio Amplifier Driver using
Digital Power Processing (DPP
TM
) Technology
Technical Information
Revision 3.3
- June 2000
GENERAL DESCRIPTION
The TA0103A is a 250W continuous average (4
Ω
), two channel Amplifier Driver
Module which uses Tripath’s proprietary Digital Power Processing (DPP
TM
)
technology. Class-T amplifiers offer both the audio fidelity of Class-AB and the
power efficiency of Class-D amplifiers.
Applications
Audio/Video
Amplifiers/Receivers
Pro-audio Amplifiers
Automobile Power Amplifiers
Subwoofer Amplifiers
Home/PC Speaker Systems
Benefits
Reduced system cost with smaller/less
expensive power supply and heat sink
Signal fidelity equal to high quality Class-
AB amplifiers
High dynamic range compatible with
digital media such as CD and DVD
Features
Class-T architecture
Proprietary Digital Power Processing
technology
Supports wide range of output power
levels
“Audiophile” Sound Quality
0.04% THD+N @ 55W, 8Ω
0.03% IHF-IM @ 36W, 8Ω
140W @ 8Ω, 0.1% THD+N,
V
S
= +54V
250W @ 4Ω, 0.1% THD+N,
V
S
= +54V
High Power
150W @ 8Ω, 1% THD+N,
V
S
= +54V
300W @ 4Ω, 1% THD+N,
V
S
= +54V
High Efficiency
92% @ 155W @ 8Ω,
V
S
= +45V
90% @ 275W @ 4Ω,
V
S
= +45V
Dynamic Range = 106 dB
Requires only N-Channel MOSFET output
transistors
High power supply rejection ratio
Mute input
Outputs short-circuit protected
Over- and under-voltage protection
Bridgeable, single-ended outputs
38-pin quad package
Supports 100kHz BW of Super Audio CD and
DVD-Audio (refer to Application Note for
specifics)
TYPICAL PERFORMANCE
THD+N versus Output Power
10
5
2
1
20Hz - 22kHz BW
f = 1kHz
BBM = 65nS
Vs = +/-54V
Av = 20.75
ST STW38NB20 MOSFET
THD+N (%)
0.5
0.2
0.1
R
L
= 8Ω
0.05
0.02
0.01
1
2
5
10
20
50
100
200
R
L
= 4Ω
Output Power (W)
1
TA0103 – Rev 3.3/06.00
Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on
Absolute Maximum Ratings
SYMBOL
Vs
V5
VN12
T
STORE
T
A
Positive 5 V Bias Supply
Reference Voltage: Nominal +12V referenced to Vsneg
Storage Temperature Range
Operating Free-air Temperature Range
PARAMETER
Supply Voltage (Vspos & Vsneg)
Value
+/-85
6
18
-40 to 150
-20 to +80
UNITS
V
V
V
ºC
ºC
Notes:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Damage will occur to the device if VN12 is not supplied or falls below the recommended
operating voltage when V
S
is within its recommended operating range.
Operating Conditions
SYMBOL
Vs
V5
VN12
Positive 5 V Bias Supply
Reference Voltage: Nominal +12V referenced to Vsneg
PARAMETER
Supply Voltage (Vspos & Vsneg)
MIN.
+/- 35
4.5
10.8
5
12
TYP.
MAX.
+/- 60
5.5
13.2
UNITS
V
V
V
Note: Recommended Operating Conditions indicate conditions for which the device is functional. See Electrical
Characteristics for guaranteed specific performance limits.
Electrical Characteristics
T
A
= 25°C. See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL
I
q
PARAMETER
+45V
-45V
+5V
VN12
Source Current @ P
OUT
= 275W, R
L
= 4Ω V
SPOS
= +45V
@ 10% THD+N
V
SNEG
= -45V
Source Current for 5V Bias Supply @ P
OUT
= 275W, R
L
= 4Ω
Source Current for VN12 Supply @ P
OUT
= 275W, R
L
= 4Ω
Under Voltage (Vspos & Vsneg)
Over Voltage (Vspos & Vsneg)
High-level Input Voltage (MUTE)
Low-level Input Voltage (MUTE)
Mute Supply Current
(no load, BBM0=BBM1=0)
+45V
-45V
+5V
VN12
High-level Output Voltage (HMUTE & OVERLOADB)
Low-level Output Voltage (HMUTE & OVERLOADB)
Over Current Sense Voltage Threshold
Gain Ratio V
OUT
/V
IN
, R
IN
= 0Ω
Offset Voltage, no load, MUTE = Logic low (before nulling)
0.67
0.75
108
300
500
0.375
3.7
17
0.5
3.5
1
0.82
+/-60
3.5
1
2
5
25
2
Quiescent Current
(no load, BBM0=BBM1=0)
MIN.
TYP.
30
36
43
210
7
7
50
80
MAX.
80
60
65
250
7.8
7.8
60
100
+/-35
UNITS
mA
mA
mA
mA
A
A
mA
mA
V
V
V
V
mA
mA
mA
mA
V
V
V
V/V
mV
I
S
I5
IVN12
Vu
Vo
V
IH
V
IL
I
DD
MUTE
V
OH
V
OL
V
TOC
A
V
Voffset
Minimum and maximum limits are guaranteed but may not be 100% tested.
2
TA0103 – Rev 3.3/06.00
Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on
Performance Characteristics – Single Ended, Vs = +54V
Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. T
A
= 25°C.
See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL
P
OUT
PARAMETER
Output Pow er
(Continuous Average/Channel)
CONDITIONS
R
L
= 8
Ω
R
L
= 4
Ω
THD+N = 1%,
R
L
= 8
Ω
R
L
= 4
Ω
P
OUT
= 55W/Channel, R
L
= 8
Ω
19kHz, 20kHz, 1:1 (IHF), R
L
= 4
Ω
P
OUT
= 36W/Channel
A Weighted, R
L
= 8
Ω
, P
OUT
=140W/Ch
0dBr = 60W, R
L
= 4
Ω
, f = 1kHz
Input Referenced, 30kHz Bandw idth
P
OUT
= 200W/Channel, R
L
= 8
Ω
A Weighted, no signal, input shorted,
DC offset nulled to zero, BBM =
145nS
THD+N = 0.1%,
MIN.
TYP.
140
250
150
300
0.04
0.02
101
82
67
92
295
MAX.
UNITS
W
W
W
W
%
%
dB
dB
dB
%
µ
V
THD + N
IHF-IM
SNR
CS
PSRR
η
e
NOUT
Total Harmonic Distortion Plus
Noise
IHF Intermodulation Distortion
Signal-to-Noise Ratio
Channel Separation
Pow er Supply Rejection Ratio
Pow er Efficiency
Output Noise Voltage
Performance Characteristics – Single Ended, Vs = +45V
Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. T
A
= 25°C.
See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL
P
OUT
PARAMETER
Output Pow er
(Continuous Average/Channel)
CONDITIONS
R
L
= 8
Ω
R
L
= 4
Ω
THD+N = 1%,
R
L
= 8
Ω
R
L
= 4
Ω
P
OUT
= 55W/Channel, R
L
= 8
Ω
19kHz, 20kHz, 1:1 (IHF), R
L
= 4
Ω
P
OUT
= 36W/Channel
A Weighted, R
L
= 8
Ω
, P
OUT
= 85W/Ch
0dBr = 60W, R
L
= 4
Ω
, f = 1kHz
Input Referenced, 30kHz Bandw idth
P
OUT
= 155W/Channel, R
L
= 8
Ω
A Weighted, no signal, input shorted,
DC offset nulled to zero, BBM = 145nS
THD+N = 0.1%,
MIN.
TYP.
85
150
100
200
0.04
0.03
100
82
67
92
250
MAX.
UNITS
W
W
W
W
%
%
dB
dB
dB
%
µ
V
THD + N
IHF-IM
SNR
CS
PSRR
η
e
NOUT
Total Harmonic Distortion Plus
Noise
IHF Intermodulation Distortion
Signal-to-Noise Ratio
Channel Separation
Pow er Supply Rejection Ratio
Pow er Efficiency
Output Noise Voltage
Minimum and maximum limits are guaranteed but may not be 100% tested.
Notes:
1)
2)
V5 = +5V, VN12 = +12V referenced to V
SNEG
Test/Application Circuit Values:
D = MUR120T3 diodes, R
IN
= 22.1KΩ
R
D
= 33Ω, R
S
= 0.025Ω,R
G
= 10Ω
R
OCR1
= R
OCR2
= 0Ω, L
F
= 18uH (Amidon core T200-2)
C
F
= 0.22uF, C
D
= 0.1uF, C
IN
= 1uF, C
BY
= 0.1uF
Power Output MOSFETs, M = ST STW38NB20
BBMO=0, BBM1=1
3
TA0103 – Rev 3.3/06.00
Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on
Pin Description
Pin
1
2
3
4
5, 6
7, 8
9, 12
10, 11
13, 14
15, 16
17, 30
18, 29
19
20, 27
21, 26
22, 25
23
24
28
31, 32
33, 34
35
36, 37, 38
Function
AGND
OVERLOADB
V5
MUTE
IN2, IN1
BBM0, BBM1
GNDKELVIN1,
GNDKELVIN2
OCR2, OCR1
OCS1L+, OCS1L-
OCS1H-, OCS1H+
LO1COM,
LO2COM
FDBKN1;FDBKN2
VN12
LO1, LO2
HO1COM, HO2COM
HO1, HO2
V
SPOS
V
SNEG
PGND
OCS2L-, OCS2L+
OCS2H-, OCS2H+
HMUTE
NC
Description
Analog Ground
Logic output. When low, indicates that the level of the input signal has
overloaded the amplifier.
Positive 5 Volts
Logic input. When high, both amplifiers are muted. When low (grounded),
both amplifiers are fully operational.
Single-ended input (Channel 1 & 2)
Break-before-make timing control
Kelvin connection to speaker ground (Channel 1 & 2)
Over-current threshold adjustment (Channel 1 & 2)
Over Current Sense resistor, Channel 1 low-side
Over Current Sense resistor, Channel 1 high-side
Kelvin connection to source of low-side transistor (Channel 1 & 2)
Feedback (Channel 1 & 2)
Voltage: +12 V from V
SNEG
. Refer to Application Information section.
Low side gate drive output (Channel 1 & 2)
Kelvin connection to source of high-side transistor (Channel 1 & 2)
High side gate drive output (Channel 1 & 2)
Positive supply voltage
Negative supply voltage
Power Ground
Over Current Sense resistor, Channel 2 low-side
Over Current Sense resistor, Channel 2 high-side
Logic output. When high, indicates that the output stages of both
amplifiers are shut off and muted.
Not Connected - Must Be Left Floating
38 Pin Quad Package Pin-out
(Top View)
38
37
36
35
34
33
32
31
30
29
28
OCS2H+
1
LO2COM
FDBKN2
OCS2L+
OCS2H-
OCS2L-
HMUTE
PGND
NC
NC
NC
AGND
OVERLOADB
LO2
27
2
HO2COM
26
3
V5
HO2
V
SNEG
V
SPOS
25
4
MUTE
24
5
IN2
IN1
BBM0
GND KELVIN1
BBM1
GND KELVIN2
23
22
21
20
6
7
8
HO1
H01COM
LO1
VN12
19
OCS1H+
LO1COM
9
10
11
12
13
14
15
16
17
Figure 1
4
TA0103 – Rev 3.3/06.00
FDBKN1
18
OCS1L+
OCR2
OCR1
OCS1H-
OCS1L-
Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on
Test/Application Circuit
TA0103A
18 FDBKN1
16 OCS1H+
R
S
15 OCS1H-
M
22
C
IN
R
IN
V5
10KΩ
1MΩ
0.1 uF
1MΩ
MUTE
4
IN1
6
HO1
R
G
M
20
LO1
R
G
L
F
D
C
BY
C
F
R
D
C
D
R
L
D
C
BY
.1uF
100uF
V
SPOS
Processing
&
Modulation
21 HO1COM
13 OCS1L+
17 LO1COM
14 OCS1L-
R
S
V
SNEG
.1uF
100uF
9 GNDKELVIN1
OCR1
R
OCR1
OCR2
R
OCR2
BBM0
BBM1
7
R
S
8
33 OCS2H-
M
25
C
IN
R
IN
V5
10KΩ
1MΩ
0.1 uF
1MΩ
NC
NC
NC
V5
0.1 uF
36
37
38
3
AGnd
1
PGnd
28
IN2
5
HO2
R
G
M
27
LO2
R
G
L
F
D
C
BY
C
F
R
D
C
D
R
L
D
C
BY
100uF
11
10
2
35
OVERLOADB
HMUTE
29 FDBKN2
34 OCS2H+
V
SPOS
Processing
&
Modulation
26 HO2COM
32 OCS2L+
30 LO2COM
31 OCS2L-
R
S
V
SNEG
.1uF
100uF
12 GNDKELVIN2
23
24
19
V
SPOS
V
SNEG
VN12
NC - Not Connected (Must Be Left Floating)
Note - Heavy Lines Indicate High-Current Paths
Figure 2
5
TA0103 – Rev 3.3/06.00
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