Tri path Technol og y, I nc. - Techni cal I nformation
TAA2008
STEREO 9W (8Ω) CLASS-T™ DIGITAL AUDIO AMPLIFIER USING
DIGITAL POWER PROCESSING™ TECHNOLOGY
TECHNICAL INFORMATION
Revision 1.0 – May 2006
GENERAL DESCRIPTION
The TAA2008 is a 9W/ch continuous average two-channel Class-T Digital Audio Power Amplifier IC
using Tripath’s proprietary Digital Power Processing™ technology. The TAA2008, in a QFN package,
along with extremely high efficiency, allows for a very compact amplifier design. Class-T amplifiers
offer both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.
APPLICATIONS
FEATURES
LCD TV’s
LCD Monitors
Plasma TV’s
Computer/PC Multimedia
Battery Powered Systems
BENEFITS
Fully integrated solution with FETs
Compact packaging and board design
Reduced system cost with no heat sink
Dramatically improves efficiency versus Class-
AB
Signal fidelity equal to high quality linear
amplifiers
High dynamic range compatible with digital
media such as CD, DVD, and Internet audio
Capable of driving a wide range of load
impedances
TYPICAL PERFORMANCE
THD+N versus Output Power
10
VDD = 12V
f = 1kHz
5 A = 12V/V
V
BW = 22Hz - 20kHz(AES17)
2
R
L
=16Ω
1
R
L
=8Ω
R
L
=6Ω
R
L
=4Ω
Class-T architecture
Single Supply Operation
“Audiophile” Quality Sound
0.025% THD+N @ 5W, 8Ω
0.1% IHF-IM @ 1W, 8Ω
6.3W @ 8Ω, 0.1% THD+N
3.5W @ 16Ω, 0.1% THD+N
High Power
14.25W @ 6Ω, 10% THD+N
9W @ 8Ω, 10% THD+N
5W @ 16Ω, 10% THD+N
Extremely High Efficiency
89% @ 5W, 16Ω
86% @ 9W, 8Ω
Dynamic Range = 98.5 dB
Mute and Sleep modes
Improved turn-on & turn-off pop
suppression
Over-current protection with automatic
restart circuit
Over-temperature protection
Space saving 32-pin 8mm x 8mm x 1mm
QFN package with exposed pad
REF
OVRLDB
AGND2
V5A
OAOUT1
INV1
MUTE
N
C
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
AGND1
V5D
DCAP1
DCAP2
5VGEN
CPUMP
PGND1
VDDA
0.5
0.2
0.1
0.05
OAOUT2
INV2
BIASCAP
AGND3
SLEEP
FAULT
PGND2
DGND
THD+N (%)
16
15
14
13
12
11
10
9
0.02
N
C
OUTP1
VDD1
OUTM1
OUTM2
VDD2
OUTP2
N
C
0.01
1
2
3
4
5
6
7
8
9 10
20
Output Power (W)
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TAA2008 –KLi/1.0/05.06
Tri path Technol og y, I nc. - Techni cal I nformation
A B S O L U T E M A X I M U M R A T I N G S
(Note 1)
SYMBOL
V
DD
V5
SLEEP
MUTE
T
STORE
T
A
T
J
ESD
HB
ESD
MM
Supply Voltage
Input Section Supply Voltage
SLEEP Input Voltage
MUTE Input Voltage
Storage Temperature Range
Operating Free-air Temperature Range
Junction Temperature
ESD Susceptibility – Human Body Model (Note 2)
ESD Susceptibility – Machine Model (Note 3)
PARAMETER
Value
16
6.0
-0.3 to 6.0
-0.3 to V5+0.3
-40 to 150
0 to 70
150
2000
200
UNITS
V
V
V
V
°C
°C
°C
V
V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Human body model, 100pF discharged through a 1.5KΩ resistor.
Note 3: Machine model, 220pF – 240pF discharged through all pins.
O P E R A T I N G C O N D I T I O N S
(Note 4)
SYMBOL
V
DD
V
IH
V
IL
Supply Voltage (Note 5)
High-level Input Voltage (MUTE, SLEEP)
Low-level Input Voltage (MUTE, SLEEP)
PARAMETER
MIN.
8.5
3.5
1
TYP.
12
MAX.
14.0
UNITS
V
V
V
Note 4: Recommended Operating Conditions indicate conditions for which the device is functional. See
Electrical Characteristics for guaranteed specific performance limits.
Note 5: Operation above 13.2V requires the use of low and high side schottky diodes as well as 220uF for
C
SW
. See the Application Section for additional information
THERMAL CHARACTERISTICS
SYMBOL
θ
JA
PARAMETER
Junction-to-ambient Thermal Resistance (note 6)
VALUE
22
UNITS
°C/W
Note 6: The
θ
JA
value is based on the exposed pad being soldered down to the printed circuit board. The
exposed pad must be soldered to an exposed copper area on the printed circuit board for proper thermal
and electrical performance.
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TAA2008 –KLi/1.0/05.06
Tri path Technol og y, I nc. - Techni cal I nformation
E L E C T R I C A L C H A R A C T E R I S T I C S
(Note 7)
See Test/Application Circuit. Unless otherwise specified, V
DD
= 12V, f = 1kHz, Measurement
Bandwidth = 20kHz, R
L
= 8Ω, T
A
= 25
°C,
package exposed pad soldered to the printed circuit
board.
SYMBOL
P
O
PARAMETER
Output Power
(Continuous Average/Channel)
CONDITIONS
THD+N = 0.1%
R
L
= 6Ω
R
L
= 8Ω
R
L
= 16Ω
R
L
= 6Ω
R
L
= 8Ω
R
L
= 16Ω
TBD
MIN.
TYP.
8
6.3
3.5
12
9
5
14.25
12
6.3
31
0.25
61
0.022
0.1
98.5
50
65
85
60
75
65
89
50
3.5
1
A-Weighted, input AC grounded
100
150
150
0.5
36
2
75
MAX.
UNITS
W
W
W
W
W
W
W
W
W
mA
mA
mA
%
%
dB
dB
dB
dB
dB
%
mV
V
V
µV
THD+N = 10%
VDD = 13.2V, THD+N=10%
R
L
= 6Ω
R
L
= 8Ω
R
L
= 16Ω
I
DD,MUTE
I
DD, SLEEP
I
q
THD + N
IHF-IM
SNR
CS
PSRR
η
V
OFFSET
V
OH
V
OL
e
OUT
Mute Supply Current
Sleep Supply Current
Quiescent Current
Total Harmonic Distortion Plus
Noise
IHF Intermodulation Distortion
Signal-to-Noise Ratio
Channel Separation
Power Supply Rejection Ratio
Power Efficiency
Output Offset Voltage
High-level output voltage
(FAULT & OVERLOAD)
Low-level output voltage
(FAULT & OVERLOAD)
Output Noise Voltage
MUTE = V
IH
SLEEP = V
IH
V
IN
= 0 V
P
O
= 5W/Channel
19kHz, 20kHz, 1:1 (IHF)
A-Weighted, P
OUT
= 9W, R
L
= 8Ω
f = 1 kHz
20 Hz
<
f
<
20 kHz
VDD = 9V to 13.2V
Vripple = 100mVrms, f=1kHz
P
OUT
= 5W/Channel, R
L
= 16Ω
No Load, MUTE = Logic Low
Note 7: Minimum and maximum limits are guaranteed but may not be 100% tested.
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TAA2008 –KLi/1.0/05.06
Tri path Technol og y, I nc. - Techni cal I nformation
PIN DESCRIPTION
Pin
1, 29
2, 30
3
4, 24,
27
5
6
7, 18
8
10, 12;
15, 13
11, 14
17
19
20
21,22
Function
OAOUT2, OAOUT1
INV2, INV1
BIASCAP
AGND3, AGND1,
AGND2
SLEEP
FAULT
PGND2, PGND1
DGND
OUTP2 & OUTM2;
OUTP1 & OUTM1
VDD2, VDD1
VDDA
CPUMP
5VGEN
DCAP2, DCAP1
Description
Input stage output pins.
Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with
approximately 2.4VDC bias.
Input stage bias voltage (approximately 2.4VDC).
Analog Ground
When set to logic high, device goes into low power mode. If not used, this pin
should be grounded
A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
Power Grounds (high current)
Digital Ground. Connect to AGND locally (near the TAA2008).
Bridged output pairs
Supply pins for high current H-bridges, nominally 12VDC.
Analog 12VDC. Connect to same supply as VDD1 and VDD2.
Charge pump output (nominally 10V above VDDA)
Regulated 5VDC source used to supply power to the input section (pins 23 and
28).
Charge pump switching pins. DCAP1 (pin 22) is a free running 300kHz square
wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 21) is level
shifted 10 volts above DCAP1 (pin 22) with the same amplitude (12Vpp nominal),
frequency, and phase as DCAP1.
Digital 5VDC, Analog 5VDC
Internal reference voltage; approximately 1.0 VDC.
A logic low output indicates the input signal has overloaded the amplifier.
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. This pin should be tied to GND if not used.
Not connected. Not bonded internally.
23, 28
25
26
31
9, 16, 32
V5D, V5A
REF
OVERLOADB
MUTE
NC
TAA2008 PINOUT
32-pin QFN
(Top View)
OVRLDB
OAOUT1
INV1
MUTE
30
29
AGND2
REF
V5A
NC
1
2
3
4
5
6
7
8
12
11
10
13
14
15
9
31
32
28
27
26
25
OAOUT2
INV2
BIASCAP
AGND3
SLEEP
FAULT
PGND2
DGND
24
23
22
21
20
19
18
17
AGND1
V5D
DCAP1
DCAP2
5VGEN
CPUMP
PGND1
VDDA
16
OUTM1
OUTM2
VDD2
OUTP2
NC
VDD1
OUTP1
NC
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TAA2008 –KLi/1.0/05.06
Tri path Technol og y, I nc. - Techni cal I nformation
APPLICATION / TEST CIRCUIT
T AA2008
OA OUT1
29
R
F
20K
Ω
INV 1
R
I
20K
Ω
C
A
0.1uF
(Pin 4)
5V
V DD1
V DD1
L
o
10uH, 2A
C
I
2.2uF
+
30
15
OUTP1
D
O
**
BIA SCA P
3
Proces s ing
&
Modulation
PGND1
V DD1
(Pin 18)
(Pin 18)
V DD1
L
o
10uH, 2A
C
o
0.22uF
C
Z
0.22uF
C
DO
0.01uF
R
L
8
Ω
or 16
Ω
13
OUTM1
C
o
0.22uF
R
Z
10
Ω ,
1/4W
D
O
**
PGND1
(Pin 18)
FA ULT (c onnec t to MUTE f or auto res tart)
OV ERLOA DB
V DD2
5V
MUTE
31
6
26
C
I
2.2uF
+
R
F
20K
Ω
OA OUT2
1
V DD2
L
o
10uH, 2A
INV 2
R
I
20K
Ω
2
10
OUTP2
D
O
**
25
(Pin 24)
R
RE F
8.25K
Ω
, 1%
REF
Proces s ing
&
Modulation
PGND2
V DD2
(Pin 7)
(Pin 7)
V DD2
L
o
10uH, 2A
C
o
0.22uF
C
Z
0.22uF
C
DO
0.01uF
22
+12V
1M
Ω
C
D
0.1uF
DCA P1
12
OUTM2
C
o
R
Z
0.22uF 10
Ω ,
1/4W
R
L
8
Ω
or 16
Ω
D
O
**
21
5
DCA P2
PGND2
SLEEP
CPUMP
19
(Pin 7)
N.C.
0.1uF
23
C
S
0.1uF
To Pin 20
C
S
0.1uF
+
V 5D
A GND1
V5A
A GND2
A GND3
5V
V DDA
DGND
5V GEN
17
8
20
C
P
1uF
C
S
0.1uF
C
S
0.1uF
To Pins 23,28
24
28
27
4
V DD1
PGND1
14
18
C
SW
0.1uF
+
V DD (+12V )
C
S W
**
100uF, 16V
9
16
NC
32
NC
NC
V DD2
PGND2
11
7
C
SW
0.1uF
Note: A nalog and Digital/Pow er Grounds mus t
be c onnec ted loc ally at the TA A 2008
A nalog Ground
Digital/Pow er Ground
** For V DD v oltages abov e 13.2V , output diodes (D
O
) s hould be us ed
and the v alue of C
S W
s hould be inc reas ed to 220uF. A ll Diodes are
Motorola MBRS130T3 or equiv alent.
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TAA2008 –KLi/1.0/05.06
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