GPIO ICs Series
Key Encoder IC
BU1851GUW
No.09098EAT03
●Features
1) Monitor up to 64-matrix keys
2) Under 5A Stand-by Current
3) Built-in Power On Reset
4) Ghost key rejection
●Absolute
maximum ratings
(Ta=25℃)
Item
Supply Voltage
*1
Input voltage
Storage temperature range
Package power
*1
*2
This IC is not designed to be X-ray proof.
It is prohibited to exceed the absolute maximum ratings even including +0.3 V.
Package dissipation will be reduced each 2.72mW/
o
C when the ambient temperature increases beyond 25
o
C.
R
●Operating
Conditions
Item
ot
Supply voltage range(VDD)
Input voltage range
Operating temperature range
External clock
External resistor
N
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Symbol
Value
Unit
V
VDD
VI
-0.3 ~ +4.5
-0.3 ~ VDD +0.3
*1
-55 ~ +125
272
*2
V
Tstg
PD
℃
mW
Limit
Typ
Symbol
VDD
V
IN
Topr
Fclk
Rxi
Unit
V
Min
Max
2.20
-0.2
-30
0.8
118.8
3.30
-
25
1.0
120
3.60
VDD+0.2
+85
1.2
121.2
V
℃
MHz
kΩ
●Description
Key Encoder IC can monitor up to 8x8 matrix (64 keys), which means to be adaptable to Qwerty keyboard. We adopt the
architecture that the information of the only key which status is changed, like push or release, is encoded into the 8 bits
data. This can greatly reduce the CPU load which tends to become heavier as the number of keys increase.
(Previously, all key's status is stored in the registers.)
Furthermore, auto sleep function contribute to low power consumption, when no keys are pressed. It is also equipped with
the various functions such as ghost key rejection, N-key Rollover, Built-in power on reset and oscillator.
1/12
or
comment
Condition
CLKSEL=VDD
To Xi pin, when CLKSEL=VSS
2009.09 - Rev.A
BU1851GUW
●
Pin Assignment
Technical Note
1
A
TESTM0
2
XRST
3
XO
4
XI
5
ROW0
6
TESTM3
B
CLKSEL
VDD
VDD
ROW2
ROW1
C
KINT
VDD
VSS
PORENB
ROW4
ROW3
●
Block Diagram
VDD
TESTM[3:0]
KINT
ec
N
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D
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D
KSDA
VDD
VSS
VSS
ROW6
ROW5
E
KSCL
COL6
COL4
COL2
COL0
ROW7
F
TESTM1
COL7
COL5
COL3
COL1
TESTM2
Fig.2 Pin Diagram(Top View)
XO
XI
CLKSEL
Oscillator
R
8bit
Column
Drive
KSCL
KSDA
3wire
Control
Key
Encoder
ot
Key Scan
N
3wire
Timeout
Reset
Gen
Power
On
Reset
8bit
Row
Monitor
XRST
PORENB
VSS
Fig.3 Functional Block Diagram
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© 2009 ROHM Co., Ltd. All rights reserved.
3/12
or
8bit
COL[7:0]
8bit
ROW[7:0]
2009.09 - Rev.A
BU1851GUW
●
Pin-out Functional Descriptions
Technical Note
PIN name
VDD
VSS
XRST
CLKSEL
XI
XO
I/O
-
-
I
I
I
O
Function
Power supply (Core, I/O)
GND
Reset(Low Active)
H: External clock is used
L: Internal CR oscillator is used
External clock input when “CLKSEL” is H.
120k is attached up to VDD when “CLKSEL”
is L.
Test pin
*1
Init
-
-
I
I
I
L
Cell
Type
-
-
A
KINT
KSCL
KSDA
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COL7
ot
PORENB
TESTM0
TESTM1
TESTM2
TESTM3
*1
*2
N
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C
O
I
Key Interrupt
H
I
C
A
Clock for serial interface
I/O
I
I
I
I
I
I
I
I
Serial data inout for serial interface
I
D
Row input from key matrix
(Pull-up)
I
Pull-up
E
O
O
O
O
O
O
O
O
I
Column output to key matrix
L
C
Power on reset enable (Low Active)
I
B
I
I
I
I
Test Pin
*2
R
I
Note: This pin must be open in normal operation.
Note: All these pins must be tied down to GND in normal operation.
4/12
or
B
G
F
2009.09 - Rev.A