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USB1T1105A Universal Serial Bus Peripheral Transceiver with Voltage Regulator
January 2005
Revised August 2005
USB1T1105A
Universal Serial Bus Peripheral Transceiver
with Voltage Regulator
General Description
The USB1T1105A is an Universal Serial Bus Specification Rev
2.0 compliant transceiver. The device provides an USB inter-
face for Full-Speed (12Mbit/s) USB applications. The
Output Enable: Active LOW enables the transceiver to transmit data on the bus. When
not active the transceiver is in the receive mode (CMOS level is relative to V
CCIO
)
Receive Data Output: Non-inverted CMOS level output for USB differential Input (CMOS
output level is relative to V
CCIO
). Driven LOW when SUSPN is HIGH;
RCV output is stable and preserved during SE0 condition.
Single-ended D
receiver output V
P
(CMOS level relative to V
CCIO
):
Used for external detection of SEO, error conditions, speed of connected device;
Driven HIGH when no supply connected to V
CC
and V
REG
.
Single-ended D
receiver output V
m
(CMOS level relative to V
CCIO
):
Used for external detection of SEO, error conditions, speed of connected device;
Driven HIGH when no supply connected to V
CC
and V
REG
.
Suspend:
Enables a low power state (CMOS level is relative to V
CCIO
). While the SUSPND pin is
active (HIGH) it will drive the RCV pin to logic “0” state.
MODE input (CMOS level is relative to V
CCIO
). A HIGH selects the differential input
MODE (V
po
, V
mo
) whereas a LOW enables the single-ended MODE (V
o
, V
FSEO
) see
Table 2 and Table 3
Supply Voltage for digital I/O pins (1.65V to 3.6V):
When not connected the D
and D
pins are in 3-STATE. This supply bus is totally
independent of V
CC
(5V) and V
REG
(3.3V).
3
V
p
O
4
V
m
O
5
SUSPND
I
6
MODE
I
7
V
CCIO
8
10, 9
11
12
13
NC
D
, D
V
po
/ V
o
V
mo
/ F
SEO
V
REG
(3.3V)
NC
AI/O
I
I
Data
, Data
: Differential data bus conforming to the USB standard.
Driver Data Input (CMOS level is relative to V
CCIO
); Schmitt trigger input;
see Table 2 and Table 3
Driver Data Input (CMOS level is relative to V
CCIO
); Schmitt trigger input;
see Table 2 and Table 3
Internal Regulator Option:
Regulated supply output voltage (3.0V to 3.6V) during 5V operation;
decoupling capacitor of at least 0.1
P
F is required.
Internal Regulator Option:
Used as supply voltage input (4.0V to 5.5V); can be connected directly to USB line
Vbus.
14
V
CC
(5.0V)
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2
USB1T1105A
Terminal Terminal
Number
Name
15
V
PU
(3.3V)
I/O
Terminal Description
Pull-up Supply Voltage (3.3V
r
10%):
Connect an external 1.5k
:
resistor on D
(FS data rate);
Pin function is controlled by Config input pin:
Config = LOW
V
PU
(3.3V) is floating (High Impedance) for zero pull-up current.
Config = HIGH
V
PU
(3.3V) = 3.3V; internally connected to V
REG
(3.3V).
16
Exposed
Diepad
Config
GND
I
GND
USB connect or disconnect software control input.
Configures 3.3V to external 1.5k
:
resistor on D
when HIGH.
GND supply down bonded to exposed diepad to be connected to the PCB GND.
Functional Description
The USB1T1105A transceiver is designed to convert CMOS
data into USB differential bus signal levels and to convert USB
differential bus signal to CMOS data.
To minimize EMI and noise the outputs are edge rate controlled
with the rise and fall times controlled and defined for full speed
data rates. The rise, fall times are balanced between the differ-
ential pins to minimize skew.
Table 1 describes the specific pin functionality selection. Table
2, Table 3, and Table 4 describe the specific Truth Tables for
Driver and Receiver operating functions.
The USB1T1105A also has the capability of various power sup-
ply configurations to support mixed voltage supply applications
(see Table 5) and Power Supply Configurations and Options for
detailed descriptions.
Functional Tables
TABLE 1. Function Select
SUSPND
L
L
H
H
OE
L
H
L
H
D, D
Driving &
Receiving
Receiving
(Note 1)
Driving
3-STATE
(Note 1)
RCV
Active
Active
Inactive
(Note 2)
Inactive
(Note 2)
V
p
/V
m
Active
Active
Active
Active
Function
Normal Driving
(Differential Receiver Active)
Receiving
Driving during Suspend
(Differential Receiver Inactive)
Low Power State
Note 1:
Signal levels is function of connection and/or pull-up/pull-down resistors.
Note 2:
For SUSPND = HIGH mode the differential receiver is inactive and the output RCV output is forced LOW. The out-of-suspend signaling (K) is detected via the single-
ended receiver outputs of the V
p
and V
m
pins.
TABLE 2. Driver Function (OE = L) using Differential Input Interface Mode Pin = H
V
mo
L
L
H
H
Note 3:
SE0 = Single Ended Zero
V
po
L
H
L
H
Data
SE0 (Note 3)
Differential Logic 1
Differential Logic 0
Illegal State
TABLE 3. Driver Function (OE = L) using Single-ended Input Interface Mode Pin = L
FSE0
L
L
H
H
V
o
L
H
L
H
Data
Differential Logic 0
Differential Logic 1
SE0 (Note 4)
SE0 (Note 4)
3
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USB1T1105A
Note 4:
SE0 = Single Ended Zero
TABLE 4. Receiver Function (OE = H)
D, D
Differential Logic 1
Differential Logic 0
SE0
Sharing Mode
X = Don’t Care
RCV
H
L
X
L
V
p
H
L
L
H
V
m
L
H
L
H
Power Supply Configurations and Options
The three modes of power supply operation are:
• Normal Mode: Regulated Output and Regulator Bypass
1. Regulated Output: V
CCIO
is connected and V
CC
(5.0) is
connected to 5V (4.0V to 5.5V) and the internal voltage
regulator then produces 3.3V for the USB connections.
2. Internal Regulator Bypass Mode: V
CCIO
is connected and
both V
CC
(5.5) and V
REG
(3.3) are connected to a 3.3V
source (3.0V to 3.6V).
In both cases for normal mode the V
CCIO
is an independent
voltage source (1.65V to 3.6V) that is a function of the exter-
nal circuit configuration.
• Sharing Mode: V
CCIO
is only supply connected. V
CC
and
V
REG
are not connected. In this mode the D
and D
pins are
3-STATE and the USB1T1105A allows external signals up to
3.6V to share the D
and D
bus lines. Internally the circuitry
limits leakage from D
and D
pins (maximum 10
P
A) and
V
CCIO
such that device is in low power (suspended) state.
Terminals Vbusmon and RCV are forced LOW as an indica-
tion of this mode with Vbusmon being ignored during this
state.
• Disable Mode: V
CCIO
is not connected. V
CC
is connected, or
V
CC
and V
REG
are connected. 0V to 3.3V in this mode D
and
D
are 3-STATE and V
PU
is HIGH Impedance (switch is
turned off). The USB1T1105A allows external signals up to
3.6V to share the D
and D
bus lines. Internally the circuitry
limits leakage from D
and D
terminals (maximum 10
P
A).
A summary of the Supply Configurations is described in Table 5.
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