CY2292
Three PLL General Purpose
EPROM Programmable Clock Generator
Three PLL General Purpose EPROM Programmable Clock Generator
Features
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Benefits
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Three integrated phase locked loops (PLLs)
Erasable programmable read only memory (EPROM)
programmability
Factory programmable (CY2292) or field programmable
(CY2292F) device options
Low-skew, low-jitter, high accuracy outputs
Power management options (shutdown, OE, suspend)
Frequency select option
Smooth slewing on CPUCLK
Configurable 3.3 V or 5 V operation
16-pin small-outline integrated circuit (SOIC) package
(CY2292F also in TSSOP)
Generates up to three custom frequencies from one external
source
Easy customization and fast turnaround
Programming support available for all opportunities
Supports low power applications
Eight user selectable frequencies on CPU PLL
Allows downstream PLLs to stay locked on CPUCLK output
Industry standard packaging saves on board space
Selector Guide
Part Number
CY2292SC, SL, SXC, SXL
CY2292SI, SXI
CY2292F, FXC, FZX
CY2292FXI, FZXI
Input Frequency Range
Output Frequency Range
Specifics
Factory programmable
Commercial temperature
10 MHz to 25 MHz (external crystal) 76.923 kHz to 100 MHz (5 V)
1 MHz to 30 MHz (reference clock) 76.923 kHz to 80 MHz (3.3 V)
10 MHz to 25 MHz (external crystal) 76.923 kHz to 90 MHz (5 V)
Factory programmable
1 MHz to 30 MHz (reference clock) 76.923 kHz to 66.6 MHz (3.3 V) Industrial temperature
10 MHz to 25 MHz (external crystal) 76.923 kHz to 90 MHz (5 V)
Field programmable
1 MHz to 30 MHz (reference clock) 76.923 kHz to 66.6 MHz (3.3 V) Commercial temperature
10 MHz to 25 MHz (external crystal) 76.923 kHz to 80 MHz (5 V)
Field programmable
1 MHz to 30 MHz (reference clock) 76.923 kHz to 60.0 MHz (3.3 V) Industrial temperature
Logic Block Diagram
XTALIN
XTALOUT
S0
S1
S2 / SUSPEND
MUX
UPLL
( 10 BIT)
/1,2,4,8
/1,2,3,4,5,6
/8,10,12,13
/20,24,26,40
/48,52,96, 104
OSC.
CPLL
( 8 BIT)
/1,2,4
XBUF
CPUCLK
CLKA
CLKB
CLKC
CLKD
SPLL
( 8 BIT)
SHUTDOWN
/
OE
CONFIG
EPROM
Cypress Semiconductor Corporation
Document Number: 38-07449 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 21, 2012
CY2292
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Operation ........................................................................... 4
Output Configuration ....................................................... 4
Power Saving Features .................................................... 4
CyClocks Software ........................................................... 4
Cypress FTG Programmer ............................................... 4
Custom Configuration Request Procedure .................... 4
Maximum Ratings ............................................................. 5
Operating Conditions ....................................................... 5
Electrical Characteristics, Commercial 5.0 V ................. 5
Electrical Characteristics, Commercial 3.3 V ................. 5
Electrical Characteristics, Industrial 5.0 V ..................... 6
Electrical Characteristics, Industrial 3.3 V ..................... 6
Switching Characteristics, Commercial 5.0 V ................ 7
Switching Characteristics, Commercial 3.3 V ................ 7
Switching Characteristics, Industrial 5.0 V .................... 8
Switching Characteristics, Industrial 3.3 V .................... 9
Switching Waveforms .................................................... 10
Test Circuit ...................................................................... 11
Ordering Information ...................................................... 11
Possible Configurations ............................................. 11
Ordering Code Definition ............................................... 12
Package Characteristics ................................................ 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................ 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC
®
Solutions ....................................................... 16
Document Number: 38-07449 Rev. *I
Page 2 of 16
CY2292
Pinouts
Figure 1. CY2292 – 16-Pin SOIC and TSSOP
CLKC
VDD
GND
XTALIN
XTALOUT
XBUF
CLKD
CPUCLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHUTDOWN/OE
S2/SUSPEND
VDD
S1
S0
GND
CLKA
CLKB
Pin Definitions
Name
CLKC
V
DD
GND
XTALIN
[1]
XTALOUT
[1, 2]
XBUF
CLKD
CPUCLK
CLKB
CLKA
S0
S1
S2/SUSPEND
SHUTDOWN/OE
Pin Number
CY2292
1
2, 14
3, 11
4
5
6
7
8
9
10
12
13
15
16
Configurable clock output C.
Voltage supply.
Ground.
Reference crystal input or external reference clock input.
Reference crystal feedback.
Buffered reference clock output.
Configurable clock output D.
CPU frequency clock output.
Configurable clock output B.
Configurable clock output A.
CPU clock select input, bit 0.
CPU clock select input, bit 1.
CPU clock select input, bit 2. Optionally enables suspend feature when LOW.
Places outputs in tristate
[3]
condition and shuts down chip when LOW. Optionally, only
places outputs in tristate
[3]
condition and does not shut down chip when LOW.
Description
Notes
1. For best accuracy, use a parallel-resonant crystal, C
LOAD
17 pF or 18 pF.
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).
3. The CY2292 has weak pull downs on all outputs. Hence, when a tristate condition is forced on the outputs, the output pins are pulled low.
Document Number: 38-07449 Rev. *I
Page 3 of 16
CY2292
Operation
The CY2292 is a third-generation family of clock generators. The
CY2292 is upwardly compatible with the industry standard
ICD2023 and ICD2028 and continues their tradition by providing
a high level of customizable features to meet the diverse clock
generation needs of modern motherboards and other
synchronous systems.
All parts provide a highly configurable set of clocks for PC
motherboard applications. Each of the four configurable clock
outputs (CLKA–CLKD) can be assigned 1 of 30 frequencies in
any combination. Multiple outputs configured for the same or
related frequencies have low (less than 500 ps) skew, in effect
providing on-chip buffering for heavily loaded signals.
The CY2292 can be configured for either 5 V or 3.3 V operation.
The internal ROM tables use EPROM technology, allowing full
customization of output frequencies. The reference oscillator is
designed for 10 MHz to 25 MHz crystals, providing additional
flexibility. No external components are required with this crystal.
Alternatively, an external reference clock of frequency between
1 MHz and 30 MHz can be used.
associated logic, while suspending an output simply forces a
tristate condition.
The CPUCLK can slew (transition) smoothly between 20 MHz
and the maximum output frequency (100 MHz at 5 V / 80 MHz at
3.3 V for commercial temperature parts or 90 MHz at
5 V / 66.6 MHz at 3.3 V for industrial temperature and for
field-programmed parts). This feature is extremely useful in
green applications, where reducing the frequency of operation
can result in considerable power savings.
CyClocks Software
CyClocks is an easy-to-use application that allows you to
configure any one of the EPROM-programmable clocks offered
by Cypress. Specify the input frequency, PLL and output
frequencies, and different functional options. Note the output
frequency ranges in this datasheet when specifying them in
CyClocks to ensure that you stay within the limits. CyClocks also
has a power calculation feature that allows you to see the power
consumption of your specific configuration. CyClocks is a sub
application located within the CyberClocks software. You can
download a copy of CyberClocks for free on the Cypress web site
at
http://www.cypress.com.
Output Configuration
The CY2292 has four independent frequency sources on-chip.
These are the reference oscillator and three PLLs. Each PLL has
a specific function. The system PLL (SPLL) provides fixed output
frequencies on the configurable outputs. The SPLL offers the
most output frequency divider options. The CPU PLL (CPLL) is
controlled by the select inputs (S0–S2) to provide eight
user-selectable frequencies with smooth slewing between
frequencies. The utility PLL (UPLL) provides the most accurate
clock. It is often used for miscellaneous frequencies not provided
by the other frequency sources.
All configurations are EPROM programmable, providing short
sample and production lead times.
Cypress FTG Programmer
The Cypress frequency timing generator (FTG) programmer is a
portable programmer designed to custom program our family of
EPROM field programmable clock devices. The FTG
programmer connects to a PC serial port and allow users of
CyClocks software to quickly and easily program any of the
CY2291F, CY2292F and CY2907F devices. The ordering code
for the Cypress FTG Programmer is CY3670. An adapter, the
CY3095, connects to the CY3670 and is required for
programming the CY2292F.
Custom Configuration Request Procedure
The CY229x are EPROM-programmable devices that may be
configured in the factory or in the field by a Cypress field
application engineer (FAE). The output frequencies requested is
matched as closely as the internal PLL divider and multiplier
options allow. All custom requests must be submitted to your
local Cypress FAE or sales representative. The method to use to
request custom configurations is:
Use CyClocks software. This software automatically calculates
the output frequencies that can be generated by the CY229x
devices and provides a print-out of final pinout which can be
submitted (in electronic or print format) to your local FAE or sales
representative.
When the custom request is processed, you receive a part
number with a 3-digit extension (for example, CY2292SC-128)
specific to the frequencies and pinout of your device. This is the
part number used for samples requests and production orders.
Power Saving Features
The SHUTDOWN/OE input tristates the outputs when pulled
LOW. If system shutdown is enabled, a LOW on this pin also
shuts off the PLLs, counters, the reference oscillator, and all
other active components. The resulting current on the V
DD
pins
is less than 50 µA (for commercial temperature or 100 µA for
industrial temperature). After leaving shutdown mode, the PLLs
have to relock. All outputs have a weak pull down so that the
outputs do not float when tristated.
[4]
The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs can be shut off in nearly any combination.
The only limitation is that if a PLL is shut off, all outputs derived
from it must also be shut off. Suspending a PLL shuts off all
Note
4. The CY2292 has weak pull downs on all outputs. Hence, when a tristate condition is forced on the outputs, the output pins are pulled low.
Document Number: 38-07449 Rev. *I
Page 4 of 16
CY2292
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage ..............................................–0.5 V to +7.0 V
DC input voltage ...........................................–0.5 V to +7.0 V
Storage temperature ................................ –65
C
to +150
C
Maximum soldering temperature (10 sec) .................. 260
C
Junction temperature.................................................. 150
C
Package power dissipation....................................... 750 mW
Static discharge voltage.............................................2000 V
(per MIL-STD-883, method 3015)
Operating Conditions
[5]
Parameter
Description
Supply voltage, 5.0 V operation
V
DD
V
DD
Supply voltage, 3.3 V operation
Commercial operating temperature, ambient
T
A
Industrial operating temperature, ambient
Maximum load capacitance 5.0 V operation
C
LOAD
Maximum load capacitance 3.3 V operation
C
LOAD
External reference crystal
f
REF
External reference clock
[6, 7, 8]
Part Numbers
All
All
CY2292 / CY2292F
CY2292I / CY2292FI
All
All
All
All
Min
4.5
3.0
0
40
–
–
10.0
1
Max
5.5
3.6
70
85
25
15
25.0
30
Unit
V
V
C
C
pF
pF
MHz
MHz
Electrical Characteristics, Commercial 5.0 V
Parameter
Description
V
OH
High level output voltage
V
OL
Low level output voltage
V
IH
High level input voltage
[9]
V
IL
I
IH
I
IL
I
OZ
I
DD
I
DDS
Low level input voltage
[9]
Input high current
Input low current
Output leakage current
V
DD
supply current
[10]
commercial
Conditions
I
OH
= 4.0 mA
I
OL
= 4.0 mA
Except crystal pins
Except crystal pins
V
IN
= V
DD
– 0.5 V
V
IN
= +0.5 V
Tristate outputs
V
DD
= V
DD
max, 5 V operation
Min
2.4
–
2.0
–
–
–
–
–
–
Typ
–
–
–
–
<1
<1
–
75
10
Max
–
0.4
–
0.8
10
10
250
100
50
Unit
V
V
V
V
µA
µA
µA
mA
µA
V
DD
power supply current in shutdown mode
[10]
Shutdown active
Electrical Characteristics, Commercial 3.3 V
Parameter
Description
High level output voltage
V
OH
V
OL
Low level output voltage
V
IH
High level input voltage
[9]
V
IL
Low level input voltage
[9]
I
IH
I
IL
I
OZ
I
DD
I
DDS
Input high current
Input low current
Output leakage current
V
DD
supply current
[10]
commercial
V
DD
power supply current in shutdown mode
[10]
Conditions
I
OH
= 4.0 mA
I
OL
= 4.0 mA
Except crystal pins
Except crystal pins
V
IN
= V
DD
– 0.5 V
V
IN
= +0.5 V
Tristate outputs
V
DD
= V
DD
max, 3.3 V operation
Shutdown active
Min
2.4
–
2.0
–
–
–
–
–
–
Typ
–
–
–
–
<1
<1
–
50
10
Max
–
0.4
–
0.8
10
10
250
65
50
Unit
V
V
V
V
µA
µA
µA
mA
µA
Notes
5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted.
6. External input reference clock must have a duty cycle between 40% and 60%, measured at V
DD
/ 2.
7. Refer to white paper “Crystal
Oscillator Topics”
for information on AC-coupling the external input reference clock.
8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is recommended
that a 150
pull up resistor to V
DD
be connected to the Xout pin.
9. Xtal inputs have CMOS thresholds.
10. Load = Max, V
IN
= 0 V or V
DD
, Typical (–104) configuration, CPUCLK = 66 MHz. Other configurations vary. Power can be approximated by the following formula
(multiply by 0.65 for 3 V operation): I
DD
= 10 + 0.06•(F
CPLL
+ F
UPLL
+ 2•F
SPLL
) + 0.27•(F
CLKA
+ F
CLKB
+ F
CLKC
+ F
CLKD
+ F
CPUCLK
+ F
XBUF
).
Document Number: 38-07449 Rev. *I
Page 5 of 16
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