74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
Rev. 2 — 18 December 2012
Product data sheet
1. General description
The 74ABT374A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT374A is an 8-bit, edge triggered register coupled to eight 3-state output
buffers. The two sections of the device are controlled independently by the clock input
(CP) and output enable input (OE) control gates.
The register is fully edge-triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors. The active LOW output enable (OE) controls all
eight 3-state buffers independent of the clock operation.
When OE is LOW, the stored data appears at the outputs. When OE is HIGH, the outputs
are in the high-impedance “OFF” state, which means they will neither drive nor load the
bus.
2. Features and benefits
8-bit positive edge triggered register
3-state output buffers
Power-on 3-state
Power-on reset
Output capability: +64 mA/32 mA
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Live insertion/extraction permitted
NXP Semiconductors
74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74ABT374AN
74ABT374AD
74ABT374ADB
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
DIP20
SO20
SSOP20
TSSOP20
Description
plastic dual in-line package; 20 leads (300 mil)
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT146-1
SOT163-1
SOT339-1
SOT360-1
Type number
74ABT374APW
40 C
to +85
C
4. Functional diagram
1
11
EN
C1
2
5
6
9
12
15
16
19
mna196
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
mna891
3
1D
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
4
7
8
13
14
17
18
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
D0
D1
D2
D3
D4
D5
D6
D7
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
CP
FF2
FF3
FF4
FF5
FF6
FF7
FF8
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aah077
Fig 3.
74ABT374A
Logic diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 18 December 2012
2 of 16
NXP Semiconductors
74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
5. Pinning information
5.1 Pinning
$%7$
2(
4
'
'
4
4
'
'
4
*1'
DDD
$%7$
9
&&
4
'
'
4
4
'
'
4
&3
2(
4
'
'
4
4
'
'
4
*1'
DDD
9
&&
4
'
'
4
4
'
'
4
&3
Fig 4.
Pin configuration for DIP20 and SO20
Fig 5.
Pin configuration for SSOP20 and TSSOP20
5.2 Pin description
Table 2.
Symbol
OE
D0, D1, D2, D3, D4, D5, D6, D7
GND
CP
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
V
CC
Pin description
Pin
1
3, 4, 7, 8, 13, 14, 17, 18
10
11
2, 5, 6, 9, 12, 15, 16, 19
20
Description
3-state output enable input (active LOW)
data input
ground (0 V)
clock pulse input (active rising edge)
3-state flip-flop output
supply voltage
6. Functional description
Table 3.
Function table
[1]
Input
OE
Load and read register
Load register and disable output
L
L
H
H
[1]
H = HIGH voltage level
h = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one setup time prior to the LOW-to-HIGH CP transition
Z = high-impedance OFF-state
= LOW-to-HIGH clock transition
Operating mode
CP
Dn
l
h
l
h
Internal
flip-flop
L
H
L
H
Output
Qn
L
H
Z
Z
74ABT374A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 18 December 2012
3 of 16
NXP Semiconductors
74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
j
T
stg
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
junction temperature
storage temperature
Conditions
[1]
Min
0.5
1.2
0.5
18
50
-
[2]
Max
+7.0
+7.0
+5.5
-
-
128
150
+150
Unit
V
V
V
mA
mA
mA
C
C
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
[1]
-
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
8. Recommended operating conditions
Table 5.
Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
t/V
T
amb
Parameter
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
input transition rise and fall rate
ambient temperature
in free air
Conditions
Min
4.5
0
2.0
-
32
-
0
40
Typ
-
-
-
-
-
-
-
-
Max
5.5
V
CC
-
0.8
-
64
10
+85
Unit
V
V
V
V
mA
mA
ns/V
C
9. Static characteristics
Table 6.
Symbol
V
IK
V
OH
Static characteristics
Parameter
Conditions
Min
input clamping voltage V
CC
= 4.5 V; I
IK
=
18
mA
HIGH-level output
voltage
V
I
= V
IL
or V
IH
V
CC
= 4.5 V; I
OH
=
3
mA
V
CC
= 5.0 V; I
OH
=
3
mA
V
CC
= 4.5 V; I
OH
=
32
mA
V
OL
LOW-level output
voltage
V
CC
= 4.5 V; I
OL
= 64 mA;
V
I
= V
IL
or V
IH
2.5
3.0
2.0
-
2.9
3.4
2.4
0.42
-
-
-
0.55
2.5
3.0
2.0
-
-
-
-
0.55
V
V
V
V
1.2
25
C
Typ
0.9
Max
-
40 C
to +85
C
Unit
Min
1.2
Max
-
V
74ABT374A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 18 December 2012
4 of 16
NXP Semiconductors
74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
Table 6.
Symbol
V
OL(pu)
I
I
I
OFF
I
O(pu/pd)
I
OZ
Static characteristics
…continued
Parameter
power-up LOW-level
output voltage
input leakage current
power-off leakage
current
Conditions
Min
V
CC
= 5.5 V; I
O
= 1 mA;
V
I
= GND or V
CC
V
CC
= 5.5 V; V
I
= V
CC
or GND
V
CC
= 0 V; V
I
or V
O
4.5 V
[2]
[1]
25
C
Typ
0.13
Max
0.55
-
-
-
-
40 C
to +85
C
Unit
Min
-
-
-
-
Max
0.55
1.0
100
50
V
A
A
A
0.01 1.0
5.0
5.0
100
50
power-up/power-down V
CC
= 2.0 V; V
O
= 0.5 V;
output current
V
I
= GND or V
CC
; OE HIGH
OFF-state output
current
V
CC
= 5.5 V; V
I
= V
IL
or V
IH
V
O
= 2.7 V
V
O
= 0.5 V
-
50
-
[3]
5.0
5.0
5.0
50
-
50
50
250
30
250
1.5
-
50
-
180
-
-
-
-
50
-
50
50
250
30
250
1.5
A
A
A
mA
A
mA
A
mA
I
LO
I
O
I
CC
output leakage current HIGH-state; V
O
= 5.5 V;
V
CC
= 5.5 V; V
I
= GND or V
CC
output current
supply current
V
CC
= 5.5 V; V
O
= 2.5 V
V
CC
= 5.5 V; V
I
= GND or V
CC
outputs HIGH-state
outputs LOW-state
outputs disabled
180 100
-
-
-
110
24
110
0.5
I
CC
additional supply
current
input capacitance
output capacitance
per input pin; V
CC
= 5.5 V;
one input at 3.4 V;
other inputs at V
CC
or GND
V
I
= 0 V or V
CC
outputs disabled; V
O
= 0 V or V
CC
[4]
-
C
I
C
O
[1]
[2]
[3]
[4]
-
-
4
7
-
-
-
-
-
-
pF
pF
For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
This parameter is valid for any V
CC
between 0 V and 2.1 V, with a transition time of up to 10 ms. From V
CC
= 2.1 V to V
CC
= 5 V
10 %
a transition time of up to 100
s
is permitted.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input at 3.4 V.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; for test circuit, see
Figure 9.
Symbol Parameter
Conditions
25
C;
V
CC
= 5.0 V
Min
f
max
t
PLH
t
PHL
t
PZH
maximum
frequency
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
OFF-state to HIGH
propagation delay
see
Figure 6
CP to Qn; see
Figure 6
CP to Qn; see
Figure 6
OE to Qn; see
Figure 8
200
1.7
2.0
1.2
Typ
300
3.4
3.8
3.5
Max
-
4.5
4.9
4.5
40 C
to +85
C;
Unit
V
CC
= 5.0 V
0.5 V
Min
200
1.7
2.0
1.2
Max
-
5.1
5.2
5.4
MHz
ns
ns
ns
74ABT374A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 18 December 2012
5 of 16
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