NCN6000
Compact Smart Card
Interface IC
The NCN6000 is an integrated circuit dedicated to the smart card
interface applications. The device handles any type of smart card
through a simple and flexible microcontroller interface. On top of that,
due to the built−in chip select pin, several couplers can be connected in
parallel. The device is particularly suited for low cost, low power
applications, with high extended battery life coming from extremely
low quiescent current.
Features
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MARKING
DIAGRAM
20
1
TSSOP−20
DTB SUFFIX
CASE 948E
1
A = Assembly Location
L
= Wafer Lot
Y = Year
W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
NCN
6000
ALYWG
G
•
100% Compatible with ISO7816−3 and EMV Standard
•
Wide Battery Supply Voltage Range: 2.7
v
Vbat
v
6.0 V
•
Programmable CRD_VCC Supply to Cope with either 3.0 V or 5.0 V
•
•
•
•
•
•
•
•
•
Card Operation
Built−in DC−DC Converter Generates the CRD_VCC Supply with a
Single External Low Cost Inductor only, providing a High Efficiency
Power Conversion
Full Control of the Power Up/Down Sequence Yields High Signal
Integrity on both the Card I/O and the Signal Lines
Programmable Card Clock Generator
Built−in Chip Select Logic allows Parallel Coupling Operation
ESD Protection on Card Pins (8.0 kV, Human Body Model)
Fault Monitoring includes Vbat
low
and Vcc
low,
providing Logic
Feedback to External CPU
Card Detection Programmable to Handle Positive or Negative
Going Input
Built−in Programmable CRD_CLK Stop Function Handles both
High or Low State
These are Pb−Free Devices**
PIN CONNECTIONS
A0 1
A1 2
PGM 3
PWR_ON 4
STATUS 5
CS 6
RESET 7
I/O 8
INT 9
CLOCK_IN 10
(Top View)
20 V
bat
19 L
out_
H
18 L
out_
L
17 PWR_GND
16 GROUND
15 CRD_V
CC
14 CRD_IO
13 CRD_CLK
12 CRD_RST
11 CRD_DET
Typical Application
•
E−Commerce Interface
•
ATM Smart Card
•
Pay TV System
ORDERING INFORMATION
Device
NCN6000DTB
ISO/EMV
NCN6000DTBG
NCN6000DTBR2
NCN6000
SMART CARD
INTERFACE
Package
TSSOP−20*
TSSOP−20*
Shipping
†
75 Units / Rail
75 Units / Rail
MICRO
CONTROLLER
TSSOP−20* 2500/Tape & Reel
NCN6000DTBR2G TSSOP−20* 2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*This package is inherently Pb−Free.
Figure 1. Simplified Application
**For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
March, 2006 − Rev. 4
Publication Order Number:
NCN6000/D
NCN6000
+5 V
V
CC
1
PB7
PB6
3
PB5
PB4
PB3
PB2
PB1
PB0
IRQ
10
XTAL
MCU
GND
4
5
6
7
8
9
2
A0
A1
PGM
U1
V
bat
L
out_H
L
out_L
C1
20
19
18
17
16
15
14
13
12
11
GND
17
18
8
4
3
2
GND
GND
1
5
7
Swa
Swb
C8
C4
CLK
RST
V
CC
GND
I/O
VPP
ISO7816
GND
C2
C3
10
mF
100 nF
GND
GND
L1
22
mH
10
mF
GND
PWR_ON PWR_GND
STATUS
CS
RESET
I/O
INT
GROUND
CRD_V
CC
CRD_IO
CRD_CLK
CRD_RST
CLOCK_IN CRD_DET
NCN6000
J1
SMARTCARD
Figure 2. Typical Application
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2
NCN6000
+V
bat
V
bat_OK
50 k
INT
9
50
ms
Delay
CARD DETECTION
POLARITY
PROGRAMMABLE
STATUS INT
500 k
Q
GND
S
R
GND
11
CRD_DET
+
−
2.0 V
V
bat
20 V
bat
+V
bat
50 k
CS
6
CLK STOP
PGM
A1
A0
3
2
1
1/1
1/2
CLOCK
DIVIDER
1/4
1/8
STATUS INT
DC−DC STATUS
ENABLE V
CC
V
bat
V
CC
DECODER
1:16
F
out
DATA
SELECT
Set_V
CC
CLOCK
DC−DC CONVERTER
3V/5V
Power Down
Active Pwr_Down
GND
FAULT
ON/OFF
V
CC
15 CRD_V
CC
19 L
out_H
18 L
out_L
17 PWR_GND
CLOCK_IN 10
16 GROUND
GND
CARD STATUS
PWR_ON
4
V
bat
SEQ 1
SEQ 2
50 k
STATUS
5
2
A
GND
V
bat_OK
I/O
8
1
V
bat
LOGIC & CARD PINS SEQUENCER
SEQ 3
V
bat_OK
CLOCK
CLK_STOP
SEQ 2
CLOCK
13 CRD_CLK
20 k
20 k
SEQ 1
DATA
I/O
V
bat
3
I/O
DATA
14 CRD_IO
1
RESET
7
2
SEQ 3
PWR_ON
RESET
12 CRD_RST
Figure 3. Block Diagram
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3
STATUS
Program Chip
PGM
RESET
A1
A0
I/O
CS
A0
I/O
L
H
L
H
L
H
L
H
L
H
L
H
Reserved
CRD_DET = Normally Open
CRD_DET = Normally Close
CRD_DET = Normally Close
CRD_DET = Normally Close
Read STATUS = 1−> Card Present/ = 0−> No Card
Read STATUS = 1−>DC−DCOK/ = 0−> DC−DC Over-
loaded
Read Vbat status−> Low = Battery OK
Read CRD_V
CC
status−> Low = CRD_V
CC
Low Voltage
L
H
L
H
Z
Z
Z
Z
STOP CRD_CLKLow
STOP CRD_CLKHigh
5 V CLOCK_IN 1/8
ENABLE CRD_CLK
5 V CLOCK_IN 1/2
5 V CLOCK_IN 1/4
3 V CLOCK_IN 1/8
5 V CLOCK_IN 1/1
3 V CLOCK_IN 1/2
3 V CLOCK_IN 1/4
3 V CLOCK_IN 1/1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
Normal Chip Operation
CARD PRESENT NO CARD DC−DC OK DC−DC OVERLOADED
STATUS PGM RESET A1
1
−
L
L
L
2
−
L
L
L
3
−
L
L
L
4
−
L
L
L
5
−
L
L
H
6
−
L
L
H
NCN6000
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Figure 4. Programming and Normal Operation Basic Timing
4
7
−
L
L
H
8
−
L
L
H
9
−
−
L
L
H
H
L
L
10
11
−
L
H
L
12
−
L
H
L
13
−
L
H
H
14
−
L
H
H
15
−
L
H
H
16
−
L
H
H
17
H/L
H
Z
L
18
H/L
H
Z
L
19
L/H
H
Z
H
20
H/L
H
Z
H
NCN6000
The programming can be achieved with the card powered
ON or OFF. The identification of the interrupt is carried out
by polling the STATUS pin, the Vbat voltage and the
DC−DC results being provided on the same pin as depicted
by the table in Figure 4. During the programming mode, the
PGM pin can be released to High since the mode is internally
latched by the Negative going transition presents on the Chip
Select pin.
INTERRUPT
ACKNOWLEDGE
50
ms
CRD_DET
INT
CS
PGM
CARD IDENTIFICATION
POLLING
CARD EXTRACTED
50
ms
High
A0
A1
STATUS
Low
Low
S1 CLEAR INTERRUPT
S2 CARD PRESENT: STATUS = 1
S3 CLEAR INTERRUPT
S4 CARD PRESENT: STATUS = 0
Figure 5. Interrupt Servicing and Card Polling
When a card is either inserted or extracted, the CRD_DET
pin signal is debounced internally prior to pull the INT pin
to Low. The built−in logic circuit automatically
accommodates positive or negative input signal slope, on
both insertion and extraction state, depending upon the
polarity defined during the initialization sequence. The
default condition is Normally Open switch, negative going
card detection. The external CPU shall acknowledge the
request by forcing CS = L which, in turn, releases the INT
pin to High upon positive going of Chip Select (Table 4).
Polling the STATUS pin as depicted in Table 3 identifies the
active card. If a card is present, the STATUS returns High,
otherwise a Low is presented pin 5. The 50
ms
digital filter
is activated during both Insertion and Extraction of the card.
The MPU shall clear the INT line when the card has been
extracted, making the interrupt function available for other
purposes. However, neither the NCN6000 operation nor the
smart card I/O line or commands are affected by the state of
the INT pin.
On the other hand, clearing the INT and reading the
STATUS register can be performed by a single read by the
MPU: states S1 and S2 can be combined in a single
instruction, the same for S3 and S4.
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5
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