Data Sheet No.PD60229 revB
IR5001S & (PbF)
UNIVERSAL ACTIVE ORING CONTROLLER
DESCRIPTION
The IR5001S is a universal high-speed controller and
N-channel power MOSFET driver for Active ORing and
reverse polarity protection applications. The output voltage
of the IR5001S is determined based on the polarity of the
voltage difference on its input terminals. In particular, if the
current flow through an N-channel ORing FET is from
source to drain, the output of the IR5001S will be pulled
high to Vcc, thus turning the Active ORing FET on. If the
current reverses direction and flows from drain to source
(due to a short-circuit failure of the source, for example),
the IC will quickly switch the Active ORing FET off. Typical
turn-off delay for the IR5001S is only 130nS, which helps
to minimize voltage sags on the redundant dc voltage.
Both inputs to the IC (INN and INP) as well as Vline
input contain integrated high voltage resistors and internal
clamps. This makes the IR5001S suitable for applications
at voltages up to 100V, and with a minimum number of
external components.
FEATURES
Controller / driver IC in an SO-8 package for
implementation of Active ORing / reverse polarity
protection using N-channel Power MOSFETs
Suitable for both input ORing (for carrier class
telecom equipment) as well as output ORing for
redundant DC-DC and AC-DC power supplies
130ns Typical Turn-Off delay time
3A Peak Turn-Off gate drive current
Asymmetrical offset voltage of the internal high-speed
comparator prevents potential oscillations at light load
Ability to withstand continuous gate short conditions
Integrated voltage clamps on both comparator inputs
allow continuous application of up to 100V
Option to be powered either directly from 36-75V
universal telecom bus (100V max), or from an
external bias supply and bias resistor
Input/Output pins to determine the state of the Active
ORing circuit and power system redundancy
APPLICATIONS
-48V/-24V Input Active ORing for carrier
class communication equipment
Reverse input polarity protection for
DC-DC power supplies
24V/48V output active ORing for
redundant AC-DC rectifiers
Low output voltage (12V, 5V, 3.3V...)
active ORing for redundant DC-DC
and AC-DC power supplies
Active ORing of multiple voltage
regulators for redundant processor
power
TYPICAL APPLICATION
+48V input
A
B
IR5001
Vline
Vcc
Vout
Gnd
INN
INP
DC
DC
FET Check Pulse
FET A Status
FETch
FETst
-48V input A
IR5001
Vline
Vcc
FETch
Fet B Status
Vout
Gnd
INN
INP
FETst
-48V input B
F 1 - Typical application of the IR5001S in - 48V input, carrier class telecommunications equipment.
Top View
Vline
1
Vcc
2
FETch
3
FETst
4
8
Vout
7
Gnd
6
INN
5
INP
PACKAGE / ORDERING INFORMATION
PKG
PART
DESIG. NUMBER
S
IR5001S
S
IR5001STR
LEADFREE
PIN
PARTS
PARTS
PART NUMBER COUNT PER TUBE PER REEL
IR5001SPbF
8
95
------
IR5001STRPbF
8
-------
2500
T&R
Oriantation
θ
JA
=128°C/W
Fig A
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IR5001S & (PbF)
ABSOLUTE MAXIMUM RATINGS
Vline Voltage
Vcc Voltage
Icc Current
INN, INP Voltage
FETch, FETst
FETst Sink Current
Junction Temperature
Storage Temperature Range
-5.0V to 100V (continuous)
-0.5V to 15VDC
5mA
-5.0V to 100V (continuous)
-0.5V to 5.5V
10mA
-40°C to 125°C
-65°C to 150°C
CAUTION:
1. Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress only rating and operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied.
2. This device is ESD sensitive. Use of standard ESD handling precautions is required.
.
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over V
line
= 36V to 100V; Vcc is decoupled with 0.1uF to
Gnd, C
L
=10nF at Vout; INP is connected to Gnd. Typical values refer to T
A
=25°C. Minimum and maximum limits
apply to T
A
= 0°C to 85°C temperature range and are 100% production-tested at both temperature extremes. Low
duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature.
PARAMETERS
Bias Section
Vline Bias Current
VCC output voltage
UVLO Section
UVLO ON Threshold Voltage
SYMBOL
Iline
TEST CONDITION
Vline=25V
Vline=36V
Vline=100V, Note 1
MIN TYP MAX UNITS
0.14 0.3 0.5
0.2
1.2
0.5
1.7
0.75
2.2
V
mA
UVLO OFF Threshold Voltage
UVLO Hysteresis
Input Comparator Section
Input Offset Voltage (VINP-
VINN)
Input Hysteresis Voltage
(INN) Input Bias Current
(INP) Input Bias Current
Vline=25V
10.2 12.5 14.1
Vline=open, VINP=0; VINN= -
0.3V
8.0 9.6 10.7
Vcc(ON)
Vcc increased until Vout switches
from LO to HI, Note 2
Vline=open, VINP=0, VINN=-
Vcc(OFF)
0.3V, Vcc is decreased until
5.6 7.2 8.8
Vout switches from HI to LO
1.6
Vos
VINP=0V and VINN Ramping up,
VOUT changes from HI to LO,
Fig.3
VINP=0,VINN ramping down,
Figures 3 and 4
VINP=0V, VINN=36V
VINN=0V, VINP=36V
-7.9
2.3
-4.0
2.8
0
Vcc(out)
V
V
mV
13
0.2
0.2
31
0.5
0.5
44
0.9
0.9
Vhyst
I(INN)
I(INP)
mA
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IR5001S & (PbF)
PARAMETERS
Output Section
High Level Output Voltage
Low Level Output Voltage
Turn-On DelayTime
Rise Time
Turn-Off Delay Time
Fall Time
FETch and FETst
FETch Sink Current
FETch Output Delay Time
FETch Threshold
FETst Threshold Voltage
FETst Low Level Output
Voltage
SYMBOL
Vout HI
Vout LO
td(on)
tr
td(off)
tf
I(FETch)
FETch_pd
Vth(FETch)
TEST CONDITION
Vline=25V, IOH=50uA,
V(INN)=-0.3V
IOL=100mA, V(INN)=+0.3V
Vout switching from LO to HI, Fig.5
Vout switching from HI to LO, Fig.5
FETch=5V
Note 1
0.9
MIN TYP MAX UNITS
10.2 11.5 14.1
0.1
5
27 45
0.09 0.7
1
110 130 170
10 26 39
-0.5 -1.1
0.8
1.2
-2
1.8
1.5
V
V
us
ms
ns
uA
us
V
mV
5k resistor from FETst to 5V logic bias.
Vth(FETst)
V(INP) = Gnd, V(INN) ramping down -525 -300 -200
from 0 until FETst switches to Low.
VOL
Isink=1mA, V(INN)=-0.5V
0
50
100
mV
Note 1:
Guaranteed by design but not tested in production.
Note 2:
Low Vcc output voltage corresponds to low UVLO voltage
PIN DESCRIPTIONS
PIN#
1
PIN SYMBOL
Vline
PIN DESCRIPTION
IC power supply pin for 36V to 75V input communications systems.
Minimum 25V has to be applied at this pin to bias the IC.
Output pin of the internal shunt regulator, or input pin for biasing the IC via
external resistor. This pin is internally regulated at 12.5V typical. A
minimum 0.1uF capacitor must be connected from this pin to Gnd of IR5001.
FET check input pin. Together with FET status output pin, the FETch pin
can be used to determine the state of the Active ORing circuit and power
system redundancy.
FET status output pin. Together with FETch input pin, the FETst pin can be
used to determine the state of the Active ORing circuit and power system
redundancy.
Positive input of internal comparator. This pin should connect to the source
of N-channel Active ORing MOSFET.
Negative input pin of internal comparator. This pin should connect to the
drain of N-channel Active ORing MOSFET.
Ground pin of the IR5001.
Output pin for the IR5001. This pin is used to directly drive the gate of the
Active Oring N-Channel MOSFET.
2
Vcc
3
FETch
4
FETst
5
INP
6
7
8
INN
Gnd
Vout
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IR5001S & (PbF)
BLOCK DIAGRAM
V
LINE
Vcc
1
2
50K
12V Shunt
Regulator
5V, V
REF
Generator
5V
1.25V
9V
8
UVLO
V
OUT
7
Gnd
5V
INP
5
12V
Level
Shifter
70K
clamp
3.5mV
28mV
70K
INN
6
clamp
5V
4
FETst
0.3V
1.25V
FETch
3
2uA
Figure 2 - Simplified block diagram of the IR5001.
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IR5001S & (PbF)
PARAMETER DEFINITION AND TIMING DIAGRAM
V
OUT
V
OUT
V
INN
(V
INP
=Gnd)
-Vos
(0,0)
V
HYST
V
OS
V
INP
- V
INN
Gnd
V
HYST
Figure 4 - Input Comparator Hysteresis Definition.
Figure 3 - Input Comparator Offset (Vos ) and Hysteresis
Voltage (Vhyst) Definition.
10ns
90mV
50mV
0
V
IN
(V
INP
- V
INN
)
t
d(on)
V
OH
90%
50%
V
OUT
V
OL
10%
t
r
Figure 5 - Dynamic Parameters.
10ns
V
INP
- V
INN
= 200mV
-50mV
-90mV
t
d(off)
t
f
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