PL138-28
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
FEATURES
•
Two differential 2.5V/3.3V LVPECL output pairs.
•
Output Frequency: ≤ 1 GHz.
•
Translates any standard single-ended or differential
input format to LVPECL output. It can accept the
following standard input formats and more:
o
LVPECL, LVCMOS, LVDS, HCSL, SSTL,
LVHSTL, CML.
•
Output Skew: 25ps (typ.).
•
Part-to-part skew: 140ps (typ.).
•
Propagation delay: 1.5ns (typ.).
•
Additive Jitter: <100 fs (typ.).
•
Operating Supply Voltage: 2.375V ~ 3.63V.
•
Operating temperature range from -40°C to 85°C.
•
Package availability: SOP-8L and TSSOP-8L.
DESCRIPTION
The PL138-28 is a high performance low-cost
1: 2 outputs Differential PECL fanout buffer.
The family of Differential LVPECL buffers are designed to
operate from a single power supply of 2.5V±5% or 3.3V±10%.
The differential input pair is designed to accept most standard
input signal levels, using an appropriate resistor bias network,
and produce a high quality set of outputs with the lowest
possible skew on the outputs, which is guaranteed for part-to-
part or lot-to lot skew.
Designed to fit in a small form-factor package, PL138
family offers up to 1GHz of output operation with very
low-power consumption, and lowest additive jitter of any
comparable device. The Output Enable feature, when
activated, allows the IC to consume less than 10µA of
current.
BLOCK DIAGRAM
Q0
CLK-IN0
CLK-IN0B
QB0
Q0
Q0B
1
8
V
CC
CLK-IN0
CLK-IN0B
V
EE
PL138-28
2
3
4
7
6
5
Q1
QB1
Q1
Q1B
8-Lead SOIC or TSSOP Package
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 11/26/13 Page 1
PL138-28
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
PIN DESCRIPTIONS
Name
Q0 ~ Q1
QB0 ~ QB1
V
EE
CLK-IN0B
CLK-IN0
Vcc
Package Pin #
SOIC-8L / TSSOP-8L
1, 3
2, 4
5
6
7
8
Type
O
O
P
I
I
P
LVPECL True output
Description
LVPECL Complementary output
Power Supply pin connection
Complementary part of differential clock input signal
True part of differential clock input signal
Power Supply pin connection
INPUT LOGIC BLOCK DIAGRAM
CLK-IN0
CLK-IN0B
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 11/26/13 Page 2
PL138-28
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
2
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
-0.5
-0.5
-65
-40
MIN.
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
110
260
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product
reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this
specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Parameter
Symbol
Min
-40°C
Typ
Max
Min
25°C
Typ
Max
Min
80°C
Typ
Max
Units
Output High Voltage*
Output Low Voltage*
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage
Input High Voltage Common Mode
Range
† ††
Input High
CLK-IN0,
Current
CLK-IN1
Input Low
Current
V
OH
V
OL
V
IH
V
IL
V
PP
V
CMR
I
IH
I
IL
2.215
1.470
2.075
1.470
150
1.2
2.320
1.610
800
2.420
1.745
2.420
1.890
1200
3.3
75
2.275
1.490
2.135
1.490
150
1.2
2.350
1.585
800
2.420
1.680
2.420
1.825
1200
3.3
75
2.275 2.35 2.420
1.490 1.585 1.680
2.135
2.420
1.490
1.825
150
800 1200
1.2
3.3
75
-75
V
V
V
V
V
V
µA
µA
-75
.
-75
Input and output parameters vary 1:1 with V
CC
V
EE
can vary +0.925V to -0.5V.
* Outputs terminated with 50
Ω
to V
CCO
– 2V.
** Single-ended input operation is limited. V
CC
≥
3V in LVPECL mode.
.
† Common mode voltage is defined as V
IH
†† For single-ended applications, the maximum input voltage for CLK-INx, CLK-INxB is V
CC
+ 0.3V
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 11/26/13 Page 3
PL138-28
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Parameter
Symbol
Min
-40°C
Typ
Max
Min
25°C
Typ
Max
Min
80°C
Typ
Max
Units
Output High Voltage*
Output Low Voltage*
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage
Input High Voltage Common Mode
Range
†
Input High
CLK-IN0,
Current
CLK-IN1
Input Low
Current
V
OH
V
OL
V
IH
V
IL
V
PP
V
CMR
I
IH
I
IL
1.415
0.670
1.275
0.670
150
1.2
1.520
0.810
800
1.620
0.945
1.620
1.090
1200
2.5
60
1.475
0.690
1.335
0.690
150
1.2
1.550
0.785
800
1.620
0.880
1.620
1.025
1200
2.5
60
1.475 1.55 1.620
0.690 0.785 0.880
1.335
1.620
0.690
1.025
150
800 1200
1.2
2.5
60
-60
V
V
V
V
V
V
µA
µA
-60
.
-60
Input and output parameters vary 1:1 with V
CC
V
EE
can vary +0.925V to -0.5V.
* Outputs terminated with 50
Ω
to V
CCO
– 2V.
V .
** Common mode voltage is defined as
IH
† For single-ended applications, the maximum input voltage for CLK-INx, CLK-INxB is V
CC
+ 0.3V
AC Electrical Characteristics
V
CC
= -3.8V to -2.375V or, V
CC
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Parameter
Symbol
f
MAX
Min
-40°C
Typ
Max
Min
25°C
Typ
Max
Min
80°C
Typ
Max
Units
Output Frequency
Propagation Delay*
Output Skew **
†
Part-to-Part Skew ***
†
Buffer Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
Output Rise/Fall Time
700
600
680
25
85
0.10
200
700
200
750
37
225
650
725
25
85
0.10
700
790
37
225
690
790
25
85
0.10
700
200
700
890
37
225
MHz
ps
ps
ps
ps
t
PD
tsk(o)
tsk(pp)
t
APJ
t
R
/ t
F
20% to 80%
700
ps
All parameters are measured at f ≤ 1000MHz, unless otherwise noted.
* Measured from the differential input crossing point to the differential output crossing point.
** Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross
points.
*** Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of
inputs on each device, the outputs are measured at the differential cross points.
†This parameter is defined in accordance with JEDEC Standard 65.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 11/26/13 Page 4
PL138-28
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
NOISE CHARACTERISTICS
(Commercial and Industrial Temperature Devices)
Parameter
Description
Additive Phase Jitter
Test Conditions
V
DD
=3.3V, Frequency=622.08MHz
Offset=12KHz ~ 20MHz
REF Input
-60
PL138-28 Output
Min.
Typ.
21
Max.
Unit
fs
t
APJ
-70
-80
-90
Phase Noise (dBc/Hz)
-100
-110
-120
-130
-140
-150
-160
100
1000
10000
100000
Offset Frequency (Hz)
1000000
10000000
100000000
When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the
buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the
Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive
Phase Jitter is as follows:
Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter)
2
2
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 11/26/13 Page 5
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