NBSG16VS
2.5 V/3.3 V SiGe Differential
Receiver/Driver with
Variable Output Swing
Description
Features
A
L
Y
W
G
•
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency up to 12 GHz Typical
Maximum Input Data Rate up to 12 Gb/s Typical
40 ps Typical Rise and Fall Times (V
CTRL
= V
CC
− 1 V)
120 ps Typical Propagation Delay (V
CTRL
= V
CC
− 1 V)
Variable Swing PECL Output with Operating Range:
V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
Variable Swing NECL Output with NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= −2.375 V to −3.465 V
Output Level (100 mV to 750 mV Peak-to-Peak Output;
V
CC
− V
EE
= 3.0 V to 3.465 V), Differential Output Only
50
W
Internal Input Termination Resistors
Compatible with Existing 2.5 V/3.3 V EP Devices
V
BB
and V
MM
Reference Voltage Output
These are Pb-Free Devices
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
June, 2014 − Rev. 14
ÇÇÇ
ÇÇÇ
ÇÇÇ
The NBSG16VS is a differential receiver/driver targeted for high
frequency applications that require variable output swing. The device
is functionally equivalent to the EP16VS device with much higher
bandwidth and lower EMI capabilities. This device may be used for
applications driving VCSEL lasers.
Inputs incorporate internal 50
W
termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS,
CML, or LVDS. The output amplitude is varied by applying a voltage
to the V
CTRL
input pin. Outputs are variable swing ECL from 100 mV
to 750 mV amplitude, optimized for operation from
V
CC
− V
EE
= 3.0 V to 3.465 V.
The V
BB
and V
MM
pins are internally generated voltage supplies
available to this device only. The V
BB
is used as a reference voltage
for single-ended NECL or PECL inputs and the V
MM
pin is used as
a reference voltage for LVCMOS inputs. For single-ended input
operation, the unused complementary differential input is connected to
V
BB
or V
MM
as a switching reference voltage. V
BB
or V
MM
may also
rebias AC-coupled inputs. When used, decouple V
BB
and V
MM
via
a 0.01
mF
capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
BB
and V
MM
outputs should be left open.
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QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAMS*
16
1
SG
16VS
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
Publication Order Number:
NBSG16VS/D
NBSG16VS
V
EE
16
VTD
D
D
VTD
V
BB
V
MM
15
14
V
EE
13
Exposed Pad (EP)
1
2
NBSG16VS
3
4
12
11
10
9
V
CC
Q
Q
V
CC
5
V
EE
6
7
8
NC V
CTRL
V
EE
Figure 1. QFN−16 Pinout
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
Name
VTD
D
I/O
−
ECL, CML,
LVCMOS,
LVDS,
LVTTL
Input
ECL, CML,
LVCMOS,
LVDS,
LVTTL
Input
−
−
−
Description
Internal 50
W
Termination Pin. See Table 2.
Inverted Differential Input. Internal 75 kW to V
EE
and 36.5 kW to V
CC
.
3
D
Noninverted Differential Input. Internal 75 kW to V
EE
.
4
5,8,13,16
6
7
9,12
10
11
14
15
−
VTD
V
EE
NC
V
CTRL
V
CC
Q
Q
V
MM
V
BB
EP
Internal 50
W
Termination Pin. See Table 2.
Negative Supply Voltage
No Connect
Output Amplitude Swing Control. Bypass Pin to V
CC
through 0.1
mF
Capacitor.
−
RSECL
Output
RSECL
Output
−
−
−
Positive Supply Voltage
Noninverted Differential Output. Typically Terminated with 50
W
to V
TT
= V
CC
− 2 V
Inverted Differential Output. Typically Terminated with 50
W
to V
TT
= V
CC
− 2 V
LVCMOS Reference Voltage Output. (V
CC
− V
EE
)/2
ECL Reference Voltage Output
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat-sinking
conduit. The pad is not electrically connected to the die but may be electrically and thermally
connected to V
EE
on the PC board.
1. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
bottom (see case drawing) must be attached to a heat-sinking conduit.
2. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to self-oscillation.
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NBSG16VS
V
CC
+
V
CTRL
0.1
mF
V
CTRL
VTD
50
W
D
D
Q
50
W
VTD
75
KW
75
KW
V
BB
V
CC
− 2 V
V
EE
V
EE
50
W
50
W
VTD
V
CC
36.5
KW
Q
Q OUT
Q OUT
V
MM
VTD
50
W
D
D
50
W
75
KW
75
KW
Q
140
W
V
BB
140
W
36.5
KW
Q
Q OUT
Q OUT
V
MM
R
VAR
V
CTRL
V
CC
+3.3 V
Figure 2. Logic Diagram/
Voltage Source Implementation
Figure 3. Alternative Voltage Source Implementation
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS
CML
LVDS
AC−COUPLED
RSECL, PECL, NECL
LVTTL
CONNECTIONS
Connect VTD and VTD to V
CC
Connect VTD and VTD Together
Bias VTD and VTD Inputs within
Common Mode Range (V
IHCMR
)
Standard ECL Termination Techniques
An external voltage should be applied to the unused
complementary differential input. Nominal voltage is
1.5 V for LVTTL.
V
MM
should be connected to the unused
complementary differential input.
LVCMOS
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor (D, D)
Internal Input Pullup Resistor (D)
ESD Protection
Moisture Sensitivity (Note 3)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
Pb-Free
Oxygen Index: 28 to 34
Value
75 kW
36.5 kW
> 2 kV
> 100 V
Level 1
UL 94 V−0 @ 0.125 in
192
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NBSG16VS
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
V
INPP
I
OUT
I
IN
I
BB
I
MM
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Negative Power Supply
Positive Input
Negative Input
Differential Input Voltage
Output Current
Input Current Through R
T
(50
W
Resistor)
V
BB
Sink/Source
V
MM
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
(Note 4)
Thermal Resistance (Junction-to-Case)
Wave Solder
Pb-Free
0 lfpm
500 lfpm
2S2P (Note 4)
|D − D|
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
V
CC
− V
EE
w
2.8 V
V
CC
− V
EE
t
2.8 V
Continuous
Surge
Static
Surge
V
I
≤
V
CC
V
I
≥
V
EE
Condition 2
Rating
3.6
−3.6
3.6
−3.6
2.8
|V
CC
− V
EE
|
25
50
45
80
1
1
−40 to +85
−65 to +150
41.6
35.2
4.0
265
Unit
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
°C
°C
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. JEDEC standards multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NBSG16VS
Table 5. DC CHARACTERISTICS, INPUT WITH VARIABLE PECL OUTPUT
(V
CC
= 2.5 V; V
EE
= 0 V) (Note 5)
−40°C
Symbol
Characteristic
Min
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Unit
POWER SUPPLY CURRENT
I
EE
Negative Power Supply Current
18
25
32
18
25
32
18
25
32
mA
VARIABLE PECL OUTPUTS
(Note 6)
V
OH
V
OL
Output HIGH Voltage
Output LOW Voltage
Max Swing
V
CTRL
= V
CC
− 600 mV
1315
645
1090
1440
765
1210
1565
885
1330
1305
605
1035
1430
725
1155
1555
845
1275
1305
600
1010
1430
720
1130
1555
840
1250
mV
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED
(Figures 9 & 11) (Note 7)
V
IH
V
IL
V
th
V
ISE
V
BB
Input HIGH Voltage
Input LOW Voltage
Input Threshold Voltage Range
(Note 8)
Single-Ended Input Voltage
(V
IH
– V
IL
)
PECL Output Voltage Reference
1200
0
950
150
1080
1140
V
CC
V
IH
−
150
V
CC
–
75
2600
1200
1200
0
950
150
1080
1140
V
CC
V
IH
−
150
V
CC
–
75
2600
1200
1200
0
950
150
1080
1140
V
CC
V
IH
−
150
V
CC
–
75
260
1200
mV
mV
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 10 & 12) (Note 9)
V
IHD
V
ILD
V
ID
V
IHCMR
I
IH
I
IL
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage
(V
IHD
– V
ILD
)
Input HIGH Voltage Common Mode
Range (Note 10) (Figure 13)
Input HIGH Current (@V
IH
)
Input LOW Current (@V
IL
)
1200
0
75
1200
30
25
V
CC
V
IHD
−
75
2600
2500
100
50
1200
0
75
1200
30
25
V
CC
V
IHD
−
75
2600
2500
100
50
1200
0
75
1200
30
25
V
CC
V
IHD
−
75
2600
2500
100
50
mV
mV
mV
mV
mA
mA
LVCMOS CONTROL PIN
V
MM
CMOS Output Voltage Reference
(V
CC
– V
EE
) / 2
1100
1250
1400
1100
1250
1400
1100
1250
1400
mV
TERMINATION RESISTORS
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V
CC
.
6. All loading with 50
W
to V
CC
− 2.0 V.
7. V
th
, V
IH
, V
IL,
and V
ISE
parameters must be complied with simultaneously.
8. V
th
is applied to the complementary input when operating in single-ended mode. V
th
= (V
IH
− V
IL
) / 2.
9. V
IHD
, V
ILD,
V
ID
and V
IHCMR
parameters must be complied with simultaneously.
10. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
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