74LCX07FT
CMOS Digital Integrated Circuits
Silicon Monolithic
74LCX07FT
1. Functional Description
•
Low-Voltage Hex Buffer with 5-V Tolerant Inputs and Outputs (Open Drain)
2. General
The 74LCX07FT is a high-performance CMOS buffer. Designed for use in 3.3 V systems and 5 V systems, it
achieves high-speed operation while maintaining the CMOS low power dissipation.
The 74LCX07FT has high performance MOS N-channel transistor. (open-drain outputs)
The device is designed for low-voltage (3.3 V) V
CC
applications, but it could be used to interface to 5 V supply*
environment for inputs.
All inputs are equipped with protection circuits against static discharge.
*I
OUT
absolute maximum rating must be observed.
3. Features
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
AEC-Q100 (Rev. H) (Note 1)
Wide operating temperature range: T
opr
= -40 to 125
Low-voltage operation: V
CC
= 1.65 to 5.5 V
High-speed operation: t
pd
= 4.5 ns (max) (V
CC
= 3.3
±
0.3 V)
Output current: I
OL
= 24 mA (min) (V
CC
= 3.0 V)
Open-drain outputs
Power-down protection provided on all inputs and outputs
Pin and function compatible with the 74 series
(74LVC/ALVC etc.) 07 type
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales
representative.
4. Packaging
TSSOP14B
Start of commercial production
©2016 Toshiba Corporation
1
2014-07
2016-09-13
Rev.5.0
74LCX07FT
5. Pin Assignment
6. Marking
7. IEC Logic Symbol
8. Truth Table
Inputs
A
L
H
Outputs
Y
L
Z
Z:
High impedance
©2016 Toshiba Corporation
2
2016-09-13
Rev.5.0
74LCX07FT
9. System Diagram(per gate)
10. Absolute Maximum Ratings (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Input diode current
Output diode current
Output current
Power dissipation
V
CC
/ground current
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
P
D
I
CC
/I
GND
T
stg
(Note 3)
(Note 2)
(Note 1)
Note
Rating
-0.5 to 6.5
-0.5 to 6.5
-0.5 to 6.5
-50
-50
50
180
±100
-65 to 150
Unit
V
V
V
mA
mA
mA
mW
mA
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
Note 1: Output in OFF state. I
OUT
absolute maximum rating must be observed. (Output in low state)
Note 2: V
OUT
< GND
Note 3: 180 mW in the range of T
a
= -40 to 85
.
From T
a
= 85 to 125
a derating factor of -3.25 mW/ shall be
applied until 50 mW.
11. Operating Ranges (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Output current
Symbol
V
CC
(Note 1)
V
IN
V
OUT
I
OL
(Note 2)
(Note 3)
(Note 4)
Operating temperature
Input rise and fall times
T
opr
dt/dv
(Note 5)
Note
Rating
1.65 to 5.5
1.5 to 5.5
0 to 5.5
0 to 5.5
32
24
12
-40 to 125
0 to 10
ns/V
V
V
mA
Unit
V
Note:
The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must
be tied to either V
CC
or GND.
Note 1: Data retention only
Note 2: V
CC
= 4.5 to 5.5 V
Note 3: V
CC
= 3.0 to 3.6 V
Note 4: V
CC
= 2.7 to 3.0 V
Note 5: V
CC
= 1.65 to 5.5 V
©2016 Toshiba Corporation
3
2016-09-13
Rev.5.0
74LCX07FT
12. Electrical Characteristics
12.1. DC Characteristics (Unless otherwise specified, T
a
= -40 to 85
)
Characteristics
High-level input voltage
Symbol
V
IH
Test Condition
V
CC
(V)
1.65 to 2.3
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
Low-level input voltage
V
IL
1.65 to 2.3
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
Low-level output voltage
V
OL
V
IN
= V
IL
I
OL
= 100
µA
I
OL
= 4 mA
I
OL
= 8 mA
I
OL
= 12 mA
I
OL
= 16 mA
I
OL
= 24 mA
I
OL
= 32 mA
Input leakage current
Output OFF-state leakage current
Power-OFF leakage current
Quiescent supply current
Quiescent supply current
I
IN
I
OZ
I
OFF
I
CC
V
IN
= 0 to 5.5 V
V
IN
= V
IH
V
OUT
= 0 to 5.5 V
V
IN
/V
OUT
= 5.5 V
V
IN
= V
CC
or GND
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
1.65 to 5.5
1.65 to 5.5
0
1.65 to 5.5
2.7 to 3.6
4.5 to 5.5
Min
V
CC
×
0.9
1.7
2.0
V
CC
×
0.7
Max
V
CC
×
0.1
0.7
0.8
V
CC
×
0.3
0.2
0.45
0.7
0.4
0.4
0.55
0.55
±5.0
±5.0
10.0
10.0
500
1.0
µA
µA
µA
µA
µA
mA
V
V
Unit
V
∆I
CC
V
IH
= V
CC
- 0.6 V
(per 1 input)
12.2. DC Characteristics (Unless otherwise specified, T
a
= -40 to 125
)
Characteristics
High-level input voltage
Symbol
V
IH
Test Condition
V
CC
(V)
1.65 to 2.3
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
Low-level input voltage
V
IL
1.65 to 2.3
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
Low-level output voltage
V
OL
V
IN
= V
IL
I
OL
= 100
µA
I
OL
= 4 mA
I
OL
= 8 mA
I
OL
= 12 mA
I
OL
= 16 mA
I
OL
= 24 mA
I
OL
= 32 mA
Input leakage current
Output OFF-state leakage current
Power-OFF leakage current
Quiescent supply current
Quiescent supply current
I
IN
I
OZ
I
OFF
I
CC
V
IN
= 0 to 5.5 V
V
IN
= V
IH
V
OUT
= 0 to 5.5 V
V
IN
/V
OUT
= 5.5 V
V
IN
= V
CC
or GND
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
1.65 to 5.5
1.65 to 5.5
0
1.65 to 5.5
2.7 to 3.6
4.5 to 5.5
Min
V
CC
×
0.9
1.7
2.0
V
CC
×
0.7
Max
V
CC
×
0.1
0.7
0.8
V
CC
×
0.3
0.2
0.6
0.85
0.6
0.6
0.8
0.8
±20.0
±20.0
40.0
40.0
5.0
5.0
µA
µA
µA
µA
mA
V
V
Unit
V
∆I
CC
V
IH
= V
CC
- 0.6 V
(per 1 input)
©2016 Toshiba Corporation
4
2016-09-13
Rev.5.0
74LCX07FT
12.3. AC Characteristics (Unless otherwise specified, T
a
= -40 to 85
)
Characteristics
Output enable time
Symbol
t
PZL
Note
Test Condition
See 12.7 AC Test Circuit,
Table 12.7.1, Fig. 12.8.1,
Table 12.8.1
V
CC
(V)
1.8
±
0.15
2.5
±
0.2
2.7
3.3
±
0.3
5.0
±
0.5
Output disable time
t
PLZ
See 12.7 AC Test Circuit,
Table 12.7.1, Fig. 12.8.1,
Table 12.8.1
1.8
±
0.15
2.5
±
0.2
2.7
3.3
±
0.3
5.0
±
0.5
Output skew
t
osZL
(Note 1)
2.7
3.3
±
0.3
Min
1.5
1.2
1.0
0.8
0.5
1.5
1.2
1.0
0.8
0.5
Max
22.0
11.0
4.4
3.7
3.0
22.0
11.0
4.4
3.7
3.0
1.0
ns
ns
Unit
ns
Note 1: Parameter guaranteed by design. (t
osZL
= |t
PZL
m-t
PZL
n|)
12.4. AC Characteristics (Unless otherwise specified, T
a
= -40 to 125
)
Characteristics
Output enable time
Symbol
t
PZL
Note
Test Condition
See 12.7 AC Test Circuit,
Table 12.7.1, Fig. 12.8.1,
Table 12.8.1
V
CC
(V)
1.8
±
0.15
2.5
±
0.2
2.7
3.3
±
0.3
5.0
±
0.5
Output disable time
t
PLZ
See 12.7 AC Test Circuit,
Table 12.7.1, Fig. 12.8.1,
Table 12.8.1
1.8
±
0.15
2.5
±
0.2
2.7
3.3
±
0.3
5.0
±
0.5
Output skew
t
osZL
(Note 1)
2.7
3.3
±
0.3
Min
1.5
1.2
1.0
0.8
0.5
1.5
1.2
1.0
0.8
0.5
Max
24.5
12.5
5.0
4.5
3.5
24.5
12.5
5.0
4.5
3.5
1.0
ns
ns
Unit
ns
Note 1: Parameter guaranteed by design. (t
osZL
= |t
PZL
m-t
PZL
n|)
12.5. Dynamic Switching Characteristics
(Unless otherwise specified, T
a
= 25
, Input: t
r
= t
f
= 2.5 ns, C
L
= 50 pF, R
L
=
500Ω
500
Ω
)
Characteristics
Quiet output maximum dynamic V
OL
Quiet output minimum dynamic V
OL
Symbol
V
OLP
|V
OLV
|
Test Condition
V
IH
= 3.3 V,V
IL
= 0 V
V
IH
= 3.3 V,V
IL
= 0 V
V
CC
(V)
3.3
3.3
Typ.
0.8
0.8
Unit
V
V
12.6. Capacitive Characteristics (Unless otherwise specified, T
a
= 25
)
Characteristics
Input capacitance
Output capacitance
Power dissipation capacitance
Symbol
C
IN
C
OUT
C
PD
(Note 1) f
IN
=10 MHz
Note
Test Condition
V
CC
(V)
3.3
3.3
3.3
Typ.
7
8
5
Unit
pF
pF
pF
Note 1: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load. Average operating current can be obtained by the equation.
I
CC(opr)
= C
PD
×
V
CC
×
f
IN
+ I
CC
/6 (per 1 gate)
©2016 Toshiba Corporation
5
2016-09-13
Rev.5.0
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