Maximum Power Dissipation (Any One Transistor) . . . . . . . 500mW
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3083 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage
which is more negative than any collector voltage in order to maintain isolation between transistors and provide normal transistor action. To
avoid undesired coupling between transistors, the substrate Terminal (5) should be maintained at either DC or signal (AC) ground. A suitable
bypass capacitor can be used to establish a signal ground.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
FOR EACH TRANSISTOR
For Equipment Design, T
A
= 25°C
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Collector-to-Base Breakdown Voltage
Collector-to-Emitter Breakdown Voltage
Collector-to-Substrate Breakdown Voltage
Emitter-to-Base Breakdown Voltage
Collector-Cutoff-Current
Collector-Cutoff-Current
DC Forward-Current Transfer Ratio (Note 3) (Figure 1)
V
(BR)CBO
V
(BR)CEO
V
(BR)CIO
V
(BR)EBO
I
CEO
I
CBO
h
FE
I
C
= 100μA, I
E
= 0
I
C
= 1mA, I
B
= 0
I
CI
= 100μA, I
B
= 0, I
E
= 0
I
E
= 500μA, I
C
= 0
V
CE
= 10V, I
B
= 0
V
CB
= 10V, I
E
= 0
V
CE
= 3V
I
C
= 10mA
I
C
= 50mA
20
15
20
5
-
-
40
40
0.65
-
-
60
24
60
6.9
-
-
76
75
0.74
0.40
450
-
-
-
-
10
1
-
-
0.85
0.70
-
V
V
V
V
μA
μA
Base-to-Emitter Voltage (Figure 2)
Collector-to-Emitter Saturation Voltage (Figures 3, 4)
Gain Bandwidth Product
V
BE
V
CE SAT
f
T
V
CE
= 3V, I
C
= 10mA
I
C
= 50mA, I
B
= 5mA
V
CE
= 3V, I
C
= 10mA
V
V
MHz
FOR TRANSISTORS Q
1
AND Q
2
(As a Differential Amplifier)
Absolute Input Offset Voltage (Figure 6)
Absolute Input Offset Current (Figure 7)
NOTE:
3. Actual forcing current is via the emitter for this test.
|V
IO
|
|I
IO
|
V
CE
= 3V, I
C
= 1mA
V
CE
= 3V, I
C
= 1mA
-
-
1.2
0.7
5
2.5
mV
μA
2
FN481.7
December 15, 2011
CA-3083
Typical Performance Curves
DC FORWARD CURRENT TRANSFER RATIO
100
V
CE
= 3V
90
T
A
= 70°C
T
A
= 25°C
T
A
= 0°C
70
BASE-TO-EMITTER VOLTAGE (V)
0.8
0.9
V
CE
= 3V
T
A
= 0°C
80
T
A
= 25°C
0.7
T
A
= 70°C
0.6
60
50
0.1
1
10
100
COLLECTOR CURRENT (mA)
0.5
0.1
1
10
COLLECTOR CURRENT (mA)
100
FIGURE 1. h
FE
vs I
C
FIGURE 2. V
BE
vs I
C
1
h
FE
= 10, T
A
= 25
o
C
COLLECTOR-TO-EMITTER
SATURATION VOLTAGE (V)
1.2
h
FE
= 10, T
A
= 70°C
1
COLLECTOR-TO-EMITTER
SATURATION VOLTAGE (V)
0.8
0.8
0.6
0.4
0.6
0.4
MAXIMUM
0.2
TYPICAL
0
1
10
COLLECTOR CURRENT (mA)
100
MAXIMUM
TYPICAL
0.2
0
1
10
COLLECTOR CURRENT (mA)
100
FIGURE 3. V
CE SAT
vs I
C
FIGURE 4. V
CE SAT
vs I
C
h
FE
= 10, T
A
= 25°C
BASE-TO-EMITTER
SATURATION VOLTAGE (V)
0.9
ABSOLUTE INPUT OFFSET VOLTAGE (mV)
1
6
V
CE
= 3V, T
A
= 25°C
5
4
3
2
1
0.8
0.7
0.6
0.5
1
10
COLLECTOR CURRENT (mA)
100
0
0.1
1
COLLECTOR CURRENT (mA)
10
FIGURE 5. V
BE SAT
vs I
C
FIGURE 6. V
IO
vs I
C
(TRANSISTORS Q
1
AND Q
2
AS A
DIFFERENTIAL AMPLIFIER)
3
FN481.7
December 15, 2011
CA-3083
Typical Performance Curves
ABSOLUTE INPUT OFFSET CURRENT (μA)
10
V
CE
= 3V, T
A
= 25°C
(Continued)
1
0.1
0.1
1
COLLECTOR CURRENT (mA)
10
FIGURE 7. I
IO
vs I
C
(TRANSISTORS Q
1
AND Q
2
AS A DIFFERENTIAL AMPLIFIER)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
