NCP398
USB Type-C VCONN
Overvoltage Protection IC
The NCP398 is an overvoltage protection device. It protects
VCONN against overvoltages in applications where VCONN is
directly derived from the VBUS supply.
At power up, the integrated power MOSFET is automatically
controlled to reduce inrush current. The IC continuously monitors
undervoltage, overvoltage and thermal events. In case of
overvoltage, a very high speed comparator opens the power
MOSFET instantaneously.
The part is enabled through the EN pin. A high level on this pin
allows forcing off the internal switch and drastically decreases the
current consumption of the NCP398 core.
Features
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MARKING
DIAGRAMS
AV MG
G
UDFN6
CASE 517AB
•
•
•
•
•
•
•
•
Over−voltage Protection up to + 28 V
On−chip Low R
dson
NMOS Transistors: Typical 200 mW
Over−voltage Lockout (OVLO)
Shutdown EN Input
Output Discharge Path
WLCSP4 Package 0.84 x 0.84 mm, 0.4p
UDFN6 Package 2 x 2 mm, 0.65p
These Parts are ROHS Devices
AV
= Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
WLCSP4
CASE 567MN
AA
A
Y
W
AA
AYW
Typical Applications
= Specific Device Code
= Assembly Location
= Year
= Work Week
•
Type−C USB
•
Smartphones
•
Tablets
PIN CONNECTIONS
IN 1
IN 2
GND 3
UDFN
6 OUT
5 OUT
4 EN
OUT
IN
EN
GND
WLCSP
(Top Views)
Figure 1. Typical Application Circuit
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2016
1
August, 2016 − Rev. 1
Publication Order Number:
NCP398/D
NCP398
Figure 2. Simplified Block Diagram, WLCSP and UDFN Packages
Table 1. CSP PINOUT DESCRIPTION
Pin
A1
B1
Pin Name
OUT
EN
Type
OUTPUT
I/O
Description
Output voltage pin.
The OUT pin must be connected to the circuitry that is to be protected (VCONN rail).
Enable pin bar.
The device enters in shutdown mode when this pin is tied high in which case the output is disconnected
from the input.
Input voltage pin.
The IN pin must be connected to the input power supply (VBUS).
Ground.
Must be connected to the system GND plane.
A2
B2
IN
GND
POWER
POWER
Table 2. DFN PINOUT DESCRIPTION
Pin
1,2
3
5,6
Pin Name
IN
GND
OUT
Type
POWER
POWER
POWER
Description
Input voltage pins.
The two IN pins must be hardwired together and are connected to the input power supply (VBUS).
Ground.
Must be connected to the system GND plane.
Output voltage pins.
The two OUT pins must be hardwired together and are connected to the circuitry that is to be protected
(VCONN rail).
Enable pin bar.
The device enters in shutdown mode when this pin is tied high in which case the output is disconnected
from the input.
DFN package back side pad. Must be connected to ground plane for thermal dissipation optimization.
4
EN
I/O
7
PAD
POWER
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NCP398
Table 3. MAXIMUM RATINGS
Rating
Minimum Voltage (All to GND)
Maximum Voltage (Ins to GND)
Maximum Voltage (All others to GND)
Maximum DC current
Thermal Resistance, Junction to Air
Operating Ambient Temperature Range
Storage Temperature Range
Junction Operating temperature
Human Body Model (HBM) ESD Rating are (Note 2)
Charged Device Model (CDM) ESD Rating are (Note 2)
Latch Up Current (Note 3)
Moisture Sensitivity
WLCSP (Note 1)
DFN (Note 1)
Symbol
V
MIN
V
INMAX
V
MAX
I
MAX
R
qJA
T
A
T
STG
T
J
ESD HBM
ESD CDM
I
LU
MSL
Value
−0.3
29
7
0.8
170
145
−40 to +85
−65 to +150
+125
2
1
100
Level 1
Unit
V
V
V
A
°C/W
°C
°C
°C
kV
kV
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The R
qJA
is highly dependent on the PCB heat sink area. As example UDFN6 R
qJA
is 220°C/W with 50 mm
2
(copper 35
mm,
1 oz) and 145°C/W
with 200 mm
2
(copper 35
mm,
2 oz).
2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114, Charged Device Model (CDM) per
JEDEC standard: JESD22−C101 Class IV.
3. Latch Up Current per JEDEC standard: JESD78 class II.
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NCP398
Table 4. ELECTRICAL CHARACTERISTICS
Min / Max limits values (−40°C < T
A
< +85°C) and V
IN
= +5 V (Unless otherwise noted). Typical values are T
A
= +25°C.
Characteristics
Input Voltage Range
Under Voltage Lockout
Under Voltage Lockout Hysteresis
Over voltage Lockout Threshold
Over voltage Lockout Threshold
hysteresis
Vin versus Vout Resistance
Symbols
V
IN
UVLO
UVLO
HYST
OVLO
(Note 4)
OVLO
HYST
R
DSON
Vin rising
Vin falling
Vin rising
Vin falling
Vin = 5 V, EN = low, 25°C, WLCSP
–40°C < T
J
< 85°C, WLCSP
Vin = 5 V, EN = low, 25°C, UDFN
–40°C < T
J
< 85°C, UDFN
Supply Quiescent Current
OFF current
Standby current
Output Discharge path
Output Discharge path level
EN
EN Voltage High
EN Voltage Low
EN Input Leakage Current
TIMINGS
Ton Time
Disable Time
OVLO Turn Off Time
TSD
Thermal shutdown
Thermal shutdown rearming
TSD
TSD rearm
−
−
150
125
−
−
°C
°C
T
ON
T
OFF
T
OVLO
Vin valid, From EN high to low, 90% Vout
From EN low to high, to 90% Vout.
R
LOAD
100
W
Vin exceeding V
OVLO
at 2 V/ms to Vout
starts decreasing. R
LOAD
100
W
−
−
−
0.3
10
100
1
−
−
ms
ms
ns
V
IH
V
IL
I
EN
0 < V
EN
< 5.5 V
1.2
−
−1
−
−
0
−
0.4
+1
V
V
mA
I
DD
I
OFF
I
STB
R
PD
V
PD
No load. EN = low
EN = high
Vin = 2.4 V
From EN = low to high or
Vin < UVLO – hysteresis to Vout = V
PD
Vout falling
Conditions
Min
−
2.4
−
5.50
−
−
−
−
−
−
−
−
8
−
Typ
−
−
50
5.65
115
190
230
230
270
40
−
−
10
0.63
Max
28
2.8
−
5.80
−
220
260
260
300
60
1.5
2.5
12
−
mA
mA
mA
kW
V
Unit
V
V
mV
V
mV
mW
4. Please contact your ON representative for additional OVLO thresholds.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCP398
Operation
The NCP398 device provides overvoltage protection
when a wrong input supply is connected or voltage ringing
appears on the input line. The internal NMOS Fet is soft
start controlled to limit inrush current into the load
(capacitors, IC wake up).
The device integrates an enable control pin, undervoltage
and overvoltage comparators, and output discharge path to
eliminate residual voltage after the turn off.
Timings Chronogram and States Description
UVLO) of the device. When Vin is below the undervoltage
comparator (UVLO) or EN is tied high, NCP398 will be in
this state.
Phase 2 corresponds to the defined time for the gate
driver soft start. Referring to the electrical parameter, this
phase is aligned to Ton time.
Phase 3 is the normal operation, with Vin valid, the part
enabled and there is no fault.
The behavior during an overvoltage condition is detailed
in the phase number 4.
The phase 1 sections described below are respectively
the OFF state (EN high) and the standby state (VIN <
Figure 3. Timings Diagram
Enable Bar Pin (EN)
Auto Discharge − R
PD
The part is enabled through the EN pin. In some diagrams
and figures, ENB refers to EN. A high level on this pin allows
forcing off the internal switch and drastically decreases the
current consumption of the NCP398 core. To exit the OFF
state, the EN pin must be tied low.
Under−voltage Lockout (UVLO)
To ensure proper operation under any conditions, the
device integrates an under−voltage lock out (UVLO)
comparator. This block has a built−in hysteresis to provide
noise immunity to transient conditions.
Over−voltage Lockout (OVLO)
When disabling the NCP398 the output gets
automatically discharged by means of the internal pull
down resistor Rpd. Once reaching the Vpd level the
discharge path is disabled. The auto−discharge is also
engaged when Vin drops below the UVLO threshold. The
auto−discharge ensures a proper power cycling of
peripherals connected to the output of the NCP398.
Thermal Shutdown Protection
To protect connected systems on V
OUT
pin from
over−voltage, a second comparator, over−voltage lock out
(OVLO), is embedded. During over−voltage condition, the
output remains disabled until the input voltage drops below
the OVLO – comparator hysteresis.
In case of internal overheating, the integrated thermal
shutdown (TSD) protection will open the internal NMOS
FET in order to instantaneously decrease the device
temperature.
Embedded hysteresis allows reengaging the NMOS FET
when the junction temperature decreases.
This OFF−ON cycle is repeated until the fault event
disappears.
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