CY7C1010DV33
2-Mbit (256 K × 8) Static RAM
2-Mbit (256 K × 8) Static RAM
Features
■
■
Functional Description
The CY7C1010DV33 is a high performance CMOS Static RAM
organized as 256 K words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and three-state drivers. Writing to the
device is accomplished by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The eight input and output pins (I/O
0
through I/O
7
) are placed in
a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1010DV33 is available in 36-pin SOJ and 44-pin
TSOP II packages with center power and ground (revolutionary)
pinout.
For a complete list of related documentation,
click here.
Pin and function compatible with CY7C1010CV33
High speed
❐
t
AA
= 10 ns
Low active power
❐
I
CC
= 90 mA at 10 ns
Low CMOS standby power
❐
I
SB2
= 10 mA
2.0 V data retention
Automatic power down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in Pb-free 36-pin SOJ and 44-pin TSOP II packages
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■
■
■
■
■
■
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
WE
OE
IO0
IO1
ROW DECODER
256K x 8
ARRAY
SENSE AMPS
IO2
IO3
IO4
IO5
IO6
COLUMN DECODER
POWER
DOWN
IO7
A12
A13
A14
A15
A16
A17
A11
Cypress Semiconductor Corporation
Document Number: 001-00062 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 19, 2014
CY7C1010DV33
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
AC Switching Characteristics ......................................... 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC® Solutions ...................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Document Number: 001-00062 Rev. *F
Page 2 of 16
CY7C1010DV33
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
-10
10
90
10
Unit
ns
mA
mA
Pin Configuration
Figure 1. 36-pin SOJ pinout
[1]
Figure 2. 44-pin TSOP II pinout
[1]
NC
NC
A
4
A
3
A
2
A
1
A
0
CE
IO
0
IO
1
V
CC
V
SS
IO
2
IO
3
WE
A
17
A
16
A
15
A
14
A
13
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A
5
A
6
A
7
A
8
OE
IO
7
IO
6
V
SS
V
CC
IO
5
IO
4
A
9
A
10
A
11
A
12
NC
NC
NC
NC
A
4
A
3
A
2
A
1
A
0
CE
IO
0
IO
1
V
CC
GND
IO
2
IO
3
WE
A
17
A
16
A
15
A
14
A
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A
5
A
6
A
7
A
8
OE
IO
7
IO
6
GND
V
CC
IO
5
IO
4
A
9
A
10
A
11
A
12
NC
NC
Note
1. NC pins are not connected on the die.
Document Number: 001-00062 Rev. *F
Page 3 of 16
CY7C1010DV33
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65
C
to +150
C
Ambient Temperature with
Power Applied ......................................... –55
C
to +125
C
Supply Voltage on
V
CC
Relative to GND
[2]
...............................–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State
[2]
................................ –0.3 V to V
CC
+ 0.3 V
DC Input Voltage
[2]
............................ –0.3 V to V
CC
+ 0.3 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Latch Up Current ................................................... > 200 mA
Operating Range
Range
Industrial
Ambient Temperature
–40C to +85C
V
CC
3.3V
0.3V
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply Current
GND < V
I
< V
CC
GND < V
OUT
< V
CC
, Output Disabled
V
CC
= Max, f = f
MAX
= 1/t
RC
100 MHz
83 MHz
66 MHz
40 MHz
I
SB1
I
SB2
Automatic CE Power-down
Current – TTL Inputs
Automatic CE Power-down
Current – CMOS Inputs
Max V
CC
, CE > V
IH
; V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max V
CC
, CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V, or V
IN
< 0.3 V, f = 0
Test Conditions
V
CC
= Min; I
OH
= –4.0 mA
V
CC
= Min; I
OL
= 8.0 mA
-10
Min
2.4
–
2.0
–0.3
–1
–1
–
–
–
–
–
–
Max
–
0.4
V
CC
+ 0.3
0.8
+1
+1
90
80
70
60
20
10
mA
mA
Unit
V
V
V
V
A
A
mA
Note
2. V
IL
(min.) = –2.0V and V
IH
(max.) = V
CC
+ 2.0V for pulse durations of less than 20 ns.
Document Number: 001-00062 Rev. *F
Page 4 of 16
CY7C1010DV33
Capacitance
Parameter
[3]
C
IN
C
OUT
Description
Input capacitance
I/O capacitance
Test Conditions
T
A
= 25
C,
f = 1 MHz, V
CC
= 3.3 V
36-pin SOJ
8
8
44-pin TSOP II Unit
8
8
pF
pF
Thermal Resistance
Parameter
[3]
JA
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch, four
layer printed circuit board
36-pin SOJ
59.17
32.63
44-pin TSOP II Unit
50.66
17.77
C/W
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
[4]
Z = 50
OUTPUT
50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
High-Z characteristics:
3.3 V
OUTPUT
5 pF
1.5 V
3.0 V
ALL INPUT PULSES
90%
10%
90%
10%
30 pF*
GND
(a)
R 317
Rise Time: 1 V/ns
(b)
Fall Time: 1 V/ns
(c)
R2
351
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) are tested using the load conditions shown in
Figure 3
(a). High-Z characteristics are tested for all speeds using the test load shown
in
Figure 3
(c).
Document Number: 001-00062 Rev. *F
Page 5 of 16
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