DATASHEET
PORTABLE CONSUMER CODEC
LOW-POWER, HIGH-FIDELITY INTEGRATED CODEC
TSCS42XX
FEATURES
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High fidelity CODEC
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2 DAC 102dB SNR
2 ADC 90dB SNR
32 bit stereo DAC and 32-bit stereo ADC
Sample rates of 8k to 96 kHz
3D stereo enhancement
12 band parametric equalizers
Dynamic Range controller
- Multi-band compressor
- Limiter
- Expander
Psychoacoustic Bass and Treble enhancement
processing
3rd Party algorithms
3W/channel 4Ω (1.5W/8Ω)
TSI DDX™ class D technology achieves low EMI and
high efficiency
>90% efficiency
Spread spectrum support for reduced EMI
Constant output power mode
Anti-Pop circuitry
Filterless architecture reduces BOM cost
35 mW output power (16Ω)
Charge-pump allows true ground centered outputs
SNR (A-Weighted, no active signal) -122dB
SNR (A-Weighted, -60db active signal) -102dB
Headphone detection logic
Analog microphone or line-in inputs
Automatic level control
1 stereo DMIC
1.7 V CODEC supports 1Vrms
Very low standby and no-signal power consumption
1.8V digital / 1.7V analog supply for low power
DESCRIPTION
The TSCS42XX is a low-power, high-fidelity integrated CODEC
with 32 bit stereo playback stereo record functionality. In addition
to a high-fidelity low-power CODEC, the device integrates the true
cap-less headphone amplifier.
The digital audio data format (I2S) works in master or slave mode
and supports all I2S formats as well as direct Bluetooth PCM
mode.
Beyond high-fidelity for portable systems, the device offers an
enriched “audio presence” through built-in audio output
processing DSP engine (AOP). The AOP supports 12 Bands of
EQ, Psychoacoustic Bass and Treble enhancement, 3D stereo
enhancement and Dynamic Range controller to support
Multi-band Compressor/Limiter capability.
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Audio Output Processing DSP Engine
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APPLICATIONS
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Bluetooth Speakers
Portable Navigation Devices
Portable Gaming Devices
Personal Media Players
Multimedia handsets
E-books
Chromebook /Tablets
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DDX™ Digital Speaker Driver
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On-chip true cap-less headphone driver
XTAL / CLK IN
XTAL OUT
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PLL
Internal
Audio Clocks
GPIO
I2C
Microphone/line-in interface
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MCLK / MCLK2 / ADCBLCK / DACBCLK
LIN1
LIN2
LIN3 / DMIC
D2S
RIN1
RIN2
MUX
RIN3 / DMIC
D2S
MICBIAS1
VREF
DAC
I2S / PCM
DSP
CAP-LESS HP L
/ LINEOUT L
ADC
MUX
INPUT
PROCESSOR
BTL
DSP
Class D
PWM
BTL
SPK Out R
I2S / PCM OUT
MUX
ADC
SPK Out L
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Low power with built in power management
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2-wire (I
2
C compatible) control interface
I
2
S data interface
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Supports Bluetooth mode
Left-Justified, Right-Justified and PCM Audio Interfaces
7x7 QFN
LIN1
MUX
LIN2
+
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LIN1
MUX
RIN2
HP DETECT
D2S
D2S
DAC
CAP-LESS HP R
/ LINEOUT R
CHARGE
PUMP
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package option
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TSCS42XX
TSCS42XX
Portable Consumer CODECs
TABLE OF CONTENTS
1. OVERVIEW ................................................................................................................................ 8
1.1. Block Diagram ...................................................................................................................................8
1.2. Audio Outputs ....................................................................................................................................8
1.3. Audio Inputs .......................................................................................................................................9
2. POWER MANAGEMENT ........................................................................................................ 10
2.1. Control Registers .............................................................................................................................10
2.1.1. Power Management Register 1 .........................................................................................10
2.1.2. Power Management 2 Register ........................................................................................11
2.2. Stopping the Master Clock ...............................................................................................................11
3. OUTPUT AUDIO PROCESSING ............................................................................................. 12
3.1. DC Removal ....................................................................................................................................12
3.2. Volume Control ................................................................................................................................13
3.2.1. Volume Control Registers ..................................................................................................14
3.3. Parametric Equalizer .......................................................................................................................15
3.3.1. Prescaler & Equalizer Filter ...............................................................................................15
3.3.2. EQ Filter Enable Register .................................................................................................16
3.3.3. DACCRAM Write/Read Registers ......................................................................................16
3.3.3.1. DAC Coefficient Write Data Low Register .......................................................16
3.3.3.2. DAC Coefficient Write Data Mid Registe ..........................................................16
3.3.3.3. DAC Coefficient WRITE Data High RegisterI ...................................................17
3.3.3.4. DAC Coefficient Read Data Low Register ........................................................17
3.3.3.5. DAC Coefficient Read Data Mid Registe ..........................................................17
3.3.3.6. DAC Coefficient Read Data High RegisteI .......................................................17
3.3.4. DACCRAM Address Register ............................................................................................18
3.3.5. DACCRAM STATUS Register ...........................................................................................18
3.3.6. Equalizer, Bass, Treble Coefficient & Equalizer Prescaler RAM .......................................18
3.4. Gain and Dynamic Range Control ...................................................................................................22
3.5. Multi-band Compressor ....................................................................................................................23
3.5.1. Overview ............................................................................................................................23
3.5.2. Multi band Compressor Registers ......................................................................................25
3.6. Limiter/Compressor Registers .........................................................................................................31
3.6.1. Limiter ................................................................................................................................31
3.6.2. Configuration ......................................................................................................................33
3.6.3. Controlling parameters .......................................................................................................33
3.6.4. Limiter/Compressor/Expander Registers ...........................................................................34
3.6.4.1. General compressor/limiter/expander control Register ....................................34
3.6.4.2. Compressor/Limiter/Expander make-up gain Register ....................................34
3.6.4.3. Compressor Threshold Register .......................................................................34
3.6.4.4. Compressor ration register ...............................................................................35
3.6.4.5. Compressor Attack Time Constant Register (Low) ..........................................35
3.6.4.6. Compressor Attack Time Constant Register (High) ..........................................35
3.6.4.7. Compressor Release Time Constant Register (Low) .......................................35
3.6.4.8. Compressor Release Time Constant Register (High) ......................................36
3.6.4.9. Limiter Threshold Register ...............................................................................36
3.6.4.10. Limiter Target Register ...................................................................................36
3.6.4.11. Limiter Attack Time Constant Register (Low) .................................................36
3.6.4.12. Limiter Attack Time Constant Register (High) ................................................37
3.6.4.13. Limiter Release Time Constant Register (Low) ..............................................37
3.6.4.14. Limiter Release Time Constant Register (High) .............................................37
3.6.4.15. Expander Threshold Register .........................................................................37
3.6.4.16. Expander Ratio Register ................................................................................38
3.6.4.17. Expander Attack Time Constant Register (Low) ............................................38
3.6.4.18. Expander Attack Time Constant Register (High) ............................................38
3.6.5. Expander Release Time Constant Register (Low) .............................................................38
3.6.6. Expander Release Time Constant Register (High) ............................................................39
3.7. Output Effects ..................................................................................................................................39
3.7.1. FX Control Register ...........................................................................................................39
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©2017 TEMPO SEMICONDCUTOR, INC.
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TSCS42XX
Portable Consumer CODECs
3.7.2. Stereo Depth (3-D) Enhancement .....................................................................................39
3.7.3. Psychoacoustic Bass Enhancement ..................................................................................40
3.7.4. Treble Enhancement ..........................................................................................................41
3.8. Mute and De-Emphasis ...................................................................................................................41
3.9. Mono Operation and Phase Inversion .............................................................................................41
3.9.1. DAC Control Register .......................................................................................................42
3.10. Analog Outputs ..............................................................................................................................42
3.10.1. Headphone Output ...........................................................................................................42
3.10.2. Speaker Output ................................................................................................................43
3.10.2.1. Speaker Volume Control Registers ................................................................43
3.10.3. DDX
TM
Class D Audio Processing ....................................................................................44
3.10.3.1. Constant Output Power Mode ........................................................................44
3.10.3.2. Under Voltage Lock Out .................................................................................47
3.10.3.3. Register ..........................................................................................................47
3.10.4. Other Output Capabilities .................................................................................................50
3.10.4.1. Audio Output Control ......................................................................................50
3.10.5. Headphone Switch ...........................................................................................................51
3.10.5.1. Headphone Switch Register ...........................................................................51
3.10.5.2. Speaker Operation .........................................................................................52
3.10.5.3. EQ Operation ..................................................................................................52
3.11. Thermal Shutdown .........................................................................................................................53
3.11.1. Algorithm description: ......................................................................................................53
3.11.2. Thermal Trip Points. .........................................................................................................53
3.11.3. Instant Cut Mode ..............................................................................................................54
3.11.4. Short Circuit Protection ....................................................................................................54
3.11.5. Thermal Shutdown Registers ...........................................................................................54
3.11.5.1. Temp Sensor Control/Status Register ............................................................54
3.11.5.2. Temp Sensor Status Register ........................................................................55
4. INPUT AUDIO PROCESSING ................................................................................................. 56
4.1. Analog Inputs ...................................................................................................................................56
4.1.1. Input Software Control Register .........................................................................................57
4.2. Mono Mixing and Output Configuration ...........................................................................................57
4.2.1. ADC D2S Input Mode Register ..........................................................................................57
4.2.2. ADC Mono, Filter, and Inversion ........................................................................................58
4.2.3. ADC Data Output Configuration .........................................................................................58
4.3. Microphone Bias ..............................................................................................................................58
4.3.1. Microphone Bias Control Register .....................................................................................59
4.4. Programmable Gain Control ............................................................................................................59
4.4.1. Input PGA Software Control Register ...............................................................................60
4.5. ADC Digital Filter .............................................................................................................................60
4.5.1. ADC Signal Path Control Register .....................................................................................61
4.5.2. ADC High Pass Filter Enable Modes .................................................................................61
4.6. Digital ADC Volume Control .............................................................................................................61
4.6.1. ADC Digital Volume Control Register ................................................................................62
4.7. Automatic Level Control (ALC) ........................................................................................................62
4.7.1. ALC Operation ..................................................................................................................62
4.7.2. ALC Control Register .........................................................................................................64
4.7.3. Peak Limiter .......................................................................................................................65
4.7.4. Input Threshold ..................................................................................................................65
4.7.5. Noise Gate Control Register ..............................................................................................65
4.8. Digital Microphone Support .............................................................................................................65
4.8.1. DMIC Clock ........................................................................................................................66
4.8.2. Digital Mic Configuration ....................................................................................................67
5. DIGITAL AUDIO AND CONTROL INTERFACES ................................................................... 69
5.1. Data Interface ..................................................................................................................................69
5.2. Master and Slave Mode Operation ..................................................................................................69
5.3. Audio Data Formats .........................................................................................................................70
5.3.1. PCM Interface ....................................................................................................................70
5.3.1.1. PCM control Registers ......................................................................................72
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©2017 TEMPO SEMICONDCUTOR, INC.
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Portable Consumer CODECs
5.3.2. Left Justified Audio Interface ..............................................................................................73
5.3.3. Right Justified Audio Interface (assuming n-bit word length) .............................................74
5.3.4. I2S Format Audio Interface ................................................................................................74
5.4. Audio Data Interface Registers ........................................................................................................75
5.4.1. I2S Interface Control Registers ..........................................................................................75
5.4.2. Data Interface Control ........................................................................................................75
5.4.3. Audio Interface Output Tri-state .........................................................................................76
5.4.4. Bit Clock and LR Clock Mode Controls ..............................................................................76
5.4.5. ADC Output Pin State ........................................................................................................78
5.4.6. Audio Interface Control 3 Register .....................................................................................78
5.4.7. Bit Clock Mode ...................................................................................................................78
5.5. I2C /Control Interface .......................................................................................................................79
5.5.1. Register Write Cycle ..........................................................................................................79
5.5.2. Multiple Write Cycle ...........................................................................................................80
5.5.3. Register Read Cycle ..........................................................................................................80
5.5.4. Multiple Read Cycle ...........................................................................................................81
5.5.5. Device Addressing and Identification .................................................................................81
5.5.6. Device Address Register ...................................................................................................81
5.5.7. Device Identification Registers ...........................................................................................81
5.5.8. Device Revision Register ...................................................................................................82
5.5.9. Register Reset ...................................................................................................................82
6. GPIO’S ..................................................................................................................................... 83
6.1. GPIO Usage Summary ....................................................................................................................83
6.2. GPIO Control Registers ...................................................................................................................83
6.2.1. GPIO Control 1 Register ....................................................................................................83
6.2.2. GPIO Control 2 Register ....................................................................................................84
7. CLOCK GENERATION ........................................................................................................... 85
7.1. On-Chip PLLs ..................................................................................................................................85
7.2. System Clock Generation ................................................................................................................86
7.2.1 PLL Dividers ........................................................................................................................86
7.2.1.1. PLL1 Control Register ....................................................................................88
7.2.1.2. PLL Control Register ......................................................................................88
7.2.1.3. PLL Reference Register ..................................................................................89
7.2.1.4. PLL1 Control Register .....................................................................................89
7.2.1.5. PLL1 Reference Clock Divider Register ...........................................................89
7.2.1.6. PLL1 Output Divider Register ...........................................................................89
7.2.1.7. PLL1 Feedback Divider Low Register ..............................................................89
7.2.1.8. PLLCTLC (122.88MHz) - PLL1 Feedback Divider High Register .....................90
7.2.1.9. PLL2 Control Register ......................................................................................90
7.2.1.10. PLL2 Reference Clock Divider Register .........................................................90
7.2.1.11. PLL2 Output Divider Register .........................................................................90
7.2.1.12. PPLL2 Feedback Divider Low Register .........................................................90
7.2.1.13. PLL2 Feedback Divider High Register ..........................................................90
7.2.1.14. PLL Control Register ......................................................................................91
7.2.2 PLL Power Down Control ....................................................................................................91
7.2.3 Audio Clock Generation ......................................................................................................91
7.2.3.1. PLL Clock Source .............................................................................................91
7.2.3.2. Internal Sample Rate Control Register ............................................................91
7.2.3.3. MCLK2 Pin ......................................................................................................93
7.2.3.4. I2S Master Mode Clock Generation ................................................................93
7.2.3.5. I2S Master Mode Sample Rate Control ...........................................................93
7.2.3.6. DAC/ADC Clock Control ..................................................................................95
7.2.3.7. TMBASE - Timebase Register .........................................................................97
8. CHARACTERISTICS ............................................................................................................... 98
8.1. Electrical Specifications ...................................................................................................................98
8.1.1. Absolute Maximum Ratings ...............................................................................................98
8.1.2. Recommended Operating Conditions ................................................................................98
8.2. Device Characteristics .....................................................................................................................99
8.3. Electrical Characteristics ................................................................................................................101
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©2017 TEMPO SEMICONDCUTOR, INC.
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TSCS42XX
Portable Consumer CODECs
9. REGISTER MAP .................................................................................................................... 102
10. PIN INFORMATION ............................................................................................................. 105
10.1. TSCS42A1 Pin Diagram ..............................................................................................................105
10.2. TSCS42A2 Pin Diagram ..............................................................................................................106
10.3. TSCS42A3 Pin Diagram ..............................................................................................................107
10.4. Pin Tables ....................................................................................................................................108
10.4.1. Power Pins .....................................................................................................................108
10.4.2. Reference Pins ..............................................................................................................108
10.4.3. Analog Input Pins ...........................................................................................................108
10.4.4. Analog Output Pins ........................................................................................................109
10.4.5. Data and Control Pins ....................................................................................................109
10.4.6. PLL Pins .........................................................................................................................109
11. PACKAGE DRAWINGS ...................................................................................................... 110
11.1. 48QFN Package Outline and Package Dimensions ....................................................................110
11.2. 40QFN Package Outline and Package Dimensions ....................................................................111
11.3. Pb Free Process- Package Classification Reflow Temperatures ................................................111
12. APPLICATION INFORMATION .......................................................................................... 112
13. ORDERING INFORMATION ............................................................................................... 112
14. DISCLAIMER ....................................................................................................................... 112
15. DOCUMENT REVISION HISTORY ..................................................................................... 113
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©2017 TEMPO SEMICONDCUTOR, INC.
V 1.1 2/17
TSCS42XX
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