driver IC suitable for driving large/medium scale dot
matrix LCD panels, and is used in personal
computers/work stations. Through the use of SST
(Super Slim TCP) technology, it is ideal for
substantially decreasing the size of the frame
section of the LCD module. The LH1562 is good
both as a segment driver and a common driver,
and it can create a low power consuming, high-
resolution LCD.
240-output LCD Segment/Common
Driver IC
• Available in a single mode (240-bit shift register)
or in a dual mode (120-bit shift register x 2)
q
Y
1
/Y
240
Single mode
w
Y
240
/Y
1
Single mode
e
Y
1
/Y
120
, Y
121
/Y
240
Dual mode
r
Y
240
/Y
121
, Y
120
/Y
1
Dual mode
The above 4 shift directions are pin-selectable
• Shift register circuits are reset when
active
PIN CONNECTIONS
269-PIN TCP
Y
1
1
Y
2
Y
3
FEATURES
•
•
•
•
•
•
Number of LCD drive outputs : 240
Supply voltage for LCD drive : +15.0 to +42.0 V
Supply voltage for the logic system : +2.5 to +5.5 V
Low power consumption
Low output impedance
Package : 269-pin TCP (Tape Carrier Package)
TOP VIEW
(Segment mode)
• Shift clock frequency
– 20 MHz (MAX.) : V
DD
= +5.0±0.5 V
– 15 MHz (MAX.) : V
DD
= +3.0 to +4.5 V
– 12 MHz (MAX.) : V
DD
= +2.5 to +3.0 V
• Adopts a data bus system
• 4-bit/8-bit parallel input modes are selectable with
a mode (MD) pin
• Automatic transfer function of an enable signal
• Automatic counting function which, in the chip
selection mode, causes the internal clock to be
stopped by automatically counting 240 bits of
input data
• Line latch circuits are reset when
active
(Common mode)
• Shift clock frequency : 4 MHz (MAX.)
• Built-in 240-bit bi-directional shift register
(divisible into 120 bits x 2)
Y
238
Y
239
Y
240
240
269 V
0R
V
12R
V
43R
V
5R
V
SS
TEST
2
TEST
1
MD
L/R
FR
EIO
1
LP
DISPOFF
XCK
DI
7
DI
6
DI
5
DI
4
DI
3
DI
2
DI
1
DI
0
EIO
2
S/C
V
DD
V
5L
V
43L
V
12L
241 V
0L
NOTE :
Doesn't prescribe TCP outline.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
CHIP SURFACE
LH1562
PIN DESCRIPTION
PIN NO.
1 to 240
241, 269
242, 268
243, 267
244, 266
245
246
247, 259
248 to 254
255
256
257
258
260
261
262
263, 264
265
SYMBOL
Y
1
-Y
240
V
0L
, V
0R
V
12L
, V
12R
V
43L
, V
43R
V
5L
, V
5R
V
DD
S/C
EIO
2
, EIO
1
DI
0
-DI
6
DI
7
XCK
LP
FR
L/R
MD
TEST
1
, TEST
2
V
SS
I/O
O
–
–
–
–
–
I
I/O
I
I
I
I
I
I
I
I
I
–
DESCRIPTION
LCD drive output
Power supply for LCD drive
Power supply for LCD drive
Power supply for LCD drive
Power supply for LCD drive
Power supply for logic system (+2.5 to +5.5 V)
Segment mode/common mode selection
Input/output for chip selection at segment mode/
Shift data input/output for shift register at common mode
Display data input at segment mode
Display data input at segment mode/Dual mode data input at common mode
Clock input for taking display data at segment mode
Control input for output of non-select level
Latch pulse input for display data at segment mode/
Shift clock input for shift register at common mode
AC-converting signal input for LCD drive waveform
Input for selecting the reading direction of display data at segment mode/
Input for selecting the shift direction of shift register at common mode
Mode selection input
Test mode selection input
Ground (0 V)
BLOCK DIAGRAM
V
0R
269
FR 260
257
EIO
1
259
EIO
2
247
LEVEL
SHIFTER
V
12R
268
V
43R
267
V
5R
266
Y
1
1
Y
2
2
Y
239
239
Y
240
240
244 V
5L
240-BIT 4-LEVEL DRIVER
243 V
43L
240
ACTIVE
CONTROL
240-BIT LEVEL SHIFTER
240
242 V
12L
241 V
0L
16
16
16
240-BIT LINE LATCH/SHIFT REGISTER
16
16
16
LP 258
XCK 256
L/R 261
MD 262
S/C 246
CONTROL
LOGIC
8
8 BITS x 2
DATA
LATCH
DATA CONTROL
SP CONVERSION & DATA CONTROL
(4 to 8 or 8 to 8)
TEST
CIRCUIT
248
DI
0
249
DI
1
250
DI
2
251
DI
3
252
DI
4
253
DI
5
254
DI
6
255
DI
7
263
TEST
1
264
TEST
2
245
V
DD
265
V
SS
2
LH1562
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK
FUNCTION
In case of segment mode, controls the selection or non-selection of the chip.
Following an LP signal input, and after the chip selection signal is input, a selection
signal is generated internally until 240 bits of data have been read in.
Once data input has been completed, a selection signal for cascade connection is
output, and the chip is non-selected.
In case of common mode, controls the input/output data of bi-directional pins.
In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel
input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel
input mode in latch circuit; after that they are put on the internal data bus 8 bits at a time.
In case of segment mode, selects the state of the data latch which reads in the data bus
Data Latch Control
signals. The shift direction is controlled by the control logic. For every 16 bits of data
read in, the selection signal shifts one bit based on the state of the control circuit.
In case of segment mode, latches the data on the data bus. The latch state of each LCD
drive output pin is controlled by the control logic and the data latch control; 240 bits of
data are read in 30 sets of 8 bits.
In case of segment mode, all 240 bits which have been read into the data latch are
simultaneously latched at the falling edge of the LP signal, and are output to the level
shifter block. In case of common mode, shifts data from the data input pin at the falling
edge of the LP signal.
Level Shifter
4-Level Driver
The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to
the driver block.
Drives the LCD drive output pins from the line latch/shift register data, and selects one of
4 levels (V
0
, V
12
, V
43
, or V
5
) based on the S/C, FR and
signals.
Controls the operation of each block. In case of segment mode, when an LP signal has
been input, all blocks are reset and the control logic waits for the selection signal output
Control Logic
from the active control block. Once the selection signal has been output, operation of the
data latch and data transmission is controlled, 240 bits of data are read in, and the chip
is non-selected. In case of common mode, controls the direction of data shift.
The circuit for testing. During normal operation, it isn't activated.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
