73M1903C
Modem Analog Front End
Simplifying System Integration
TM
DS_1903C_033
DESCRIPTION
The 73M1903C Analog Front End (AFE) IC includes
fully differential hybrid driver outputs, which connect to
the telephone line interface through a transformer-
based DAA. The receive pins are also fully differential
for maximum flexibility and performance. This
arrangement allows for the design of a high
performance hybrid circuit to improve signal to noise
performance under low receive level conditions, and
compatibility with any standard transformer intended
for PSTN communications applications.
The device incorporates a programmable sample rate
circuit to support soft modem and DSP based
implementations of all speeds up to V.92 (56 kbps).
The sampling rates supported are from 7.2 kHz to
16.0 kHz by programming the pre-scaler NCO and the
PLL NCO.
The 73M1903C device incorporates a digital host
interface that is compatible with the serial ports found
on most commercially available DSPs and processors
and exchanges both payload and control information
with the host. This interface can be configured as a
single master/slave mode or as a daisy chain mode
that allows the user to connect up to eight 73M1903C
devices to a single host for multi Analog Front End
applications, such as, central server modems.
Costs saving features of the device include an input
reference frequency circuit, which accepts a range of
crystals from 4.9-27 MHz. It also accepts external
reference clock values between 1 MHz and 40 MHz
generated by the host processor. In most
applications, this eliminates the need for a dedicated
crystal oscillator and reduces the bill of materials
(BOM).
The 73M1903C also supports two analog loop back
and one digital loop back test modes.
FEATURES
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Two pairs of software selectable transmit
differential outputs for worldwide impedance
driver implementations.
Up to 56 kbps (V.92) performance
Programmable sample rates (7.2-16.0 kHz)
Reference clock range of 1-40 MHz
Crystal frequency range of 4.9-27 MHz
Master or slave mode operation
Daisy chain configurable synchronous serial
Host interface
Low power modes
Fully differential receiver and transmitter
Drivers for transformer interface
3.0 V – 3.6 V operation
5 V tolerant I/O
Industrial temperature range (-40 to +85
°C)
JATE compliant transmit spectrum
Package option: 32-pin QFN
DATA SHEET
March 2010
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APPLICATIONS
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Central site server modems
Set Top Boxes
Personal Video Recorders (PVR)
Multifunction Peripherals (MFP)
Fax Machines
Internet Appliances
Game Consoles
Point of Sale Terminals
Automatic Teller Machines
Speaker Phones
Digital Answering Machines
RF Modems
VBG
(HYBRID)
TXAP1
TXAN1
TXAP2
TXAN2
RXAP
RXAN
Transmit
Drivers/
Filters
Analog
Sigma
Delta
Ref.
SCLK
Control
Registers
SDIN
Serial
Port
SDOUT
FS
Control
Logic
FSD
Receiver
MUX/
Filters
DAC
GPIO
HOOK
DAA
controls
Clock
Crystal
Rev. 5.0
1
73M1903C Data Sheet
DS_1903C_033
Table of Contents
1
2
Pin Description
................................................................................................................................ 4
Modem Analog Front End (MAFE) Serial Interface
........................................................................ 6
2.1 Serial Data and Control.............................................................................................................. 7
2.2 Slave Mode and DAISY CHAIN ............................................................................................... 10
2.3 Control Register Map ............................................................................................................... 12
3 System Control Registers
............................................................................................................. 13
4 GPIO Registers
.............................................................................................................................. 15
5 PLL Configuration Registers
........................................................................................................ 16
6 Clock Generation...........................................................................................................................
19
6.1 Crystal Oscillator and Prescaler NCO ...................................................................................... 19
6.2 Analog I/O ............................................................................................................................... 22
6.3 Modem Transmitter.................................................................................................................. 23
6.4 Transmit Levels ....................................................................................................................... 24
6.5 Transmit Power – dBm ............................................................................................................ 25
6.6 Modem Receiver ..................................................................................................................... 26
7 Test Modes
.................................................................................................................................... 29
7.1 Power Saving Modes ............................................................................................................... 29
8 Electrical Specifications
............................................................................................................... 30
8.1 Absolute Maximum Ratings ..................................................................................................... 30
8.2 Recommended Operating Conditions....................................................................................... 30
8.3 Digital Specifications ................................................................................................................ 31
8.3.1 DC Characteristics ........................................................................................................ 31
8.4 AC Timing ............................................................................................................................... 32
9 Analog Specifications
................................................................................................................... 33
9.1 DC Specifications .................................................................................................................... 33
9.2 AC Specifications .................................................................................................................... 33
9.3 Performance ............................................................................................................................ 34
9.3.1 Receiver ....................................................................................................................... 34
9.3.2 Transmitter ................................................................................................................... 35
10 Mechanical Drawings
.................................................................................................................... 37
11 Ordering Information.....................................................................................................................
38
Appendix A
.......................................................................................................................................... 39
73M1903C DAA Resistor Calculation Guide .................................................................................... 39
Trans-Hybrid Loss (THL) ................................................................................................................. 41
Appendix B
.......................................................................................................................................... 42
Crystal Oscillator ............................................................................................................................. 42
PLL 43
Examples of NCO Settings .............................................................................................................. 44
Example 1 ............................................................................................................................... 44
Example 2 ............................................................................................................................... 45
Example 3 ............................................................................................................................... 46
Example 4 ............................................................................................................................... 47
Revision History
.................................................................................................................................. 48
2
Rev. 5.0
DS_1903C_033
73M1903C Data Sheet
Figures
Figure 1: SCLK and
FS
with SckMode=0 ................................................................................................. 8
Figure 2: Control Frame Position versus SPOS........................................................................................ 8
Figure 3: Serial Port Timing Diagrams ..................................................................................................... 9
Figure 4: 73M1903C Host Connection in Master and Slave Modes ........................................................ 10
Figure 5: 73M1903C Daisy Chaining for Master/Slave Mode and Slave Modes ...................................... 10
Figure 6: Clock Generation .................................................................................................................... 19
Figure 7: Analog Block Diagram............................................................................................................. 22
Figure 8: Overall TX Path Frequency Response at 8 kHz Sample Rate.................................................. 23
Figure 9: Frequency Response of TX Path for DC to 4 kHz in Band Signal at 8 kHz Sample Rate.......... 24
Figure 10: Overall Receiver Frequency Response at 8 kHz Sample Rate............................................... 26
Figure 11: Rx Passband Response at 8 kHz Sample Rate ..................................................................... 27
Figure 12: RXD Spectrum of 1 kHz Tone ............................................................................................... 28
Figure 13: RXD Spectrum of 0.5 kHz, 1 kHz, 2 kHz, 3 kHz and 3.5 kHz Tones of Equal Amplitudes ....... 28
Figure 14: Serial Port Data Timing ......................................................................................................... 32
Figure 15: Typical DAA Block Diagram .................................................................................................. 39
Figure 16: Single Transmitter Arrangement ............................................................................................ 40
Figure 17: Dual transmitter arrangement ................................................................................................ 41
Figure 18: NCO Block Diagram.............................................................................................................. 42
Figure 19: PLL Block Diagram ............................................................................................................... 43
Tables
Table 1: 32 QFN Pin Description.............................................................................................................. 4
Table 2: Register Map ........................................................................................................................... 12
Table 3: Fvco and Kvco Settings at 25°C ............................................................................................... 16
Table 4: PLL Power Down ..................................................................................................................... 18
Table 5: Clock Generation Register Settings for Fxtal = 27 MHz ............................................................ 19
Table 6: Clock Generation Register Settings for Fxtal = 24.576 MHz...................................................... 20
Table 7: Clock Generation Register Settings for Fxtal = 9.216 MHz........................................................ 20
Table 8: Clock Generation Register Settings for Fxtal = 24.000 MHz...................................................... 21
Table 9: Clock Generation Register Settings for Fxtal = 25.35 MHz........................................................ 21
Table 10: Peak to RMS Ratios and Maximum Transmit.......................................................................... 25
Table 11: Receive Gain ......................................................................................................................... 26
Table 12: Absolute Maximum Ratings .................................................................................................... 30
Table 13: Recommended Operation Conditions ..................................................................................... 30
Table 14: DC Characteristics ................................................................................................................. 31
Table 15: Serial Interface Timing ........................................................................................................... 32
Table 16: Reference Voltage Specifications ........................................................................................... 33
Table 17: Maximum Transmit Levels ...................................................................................................... 33
Table 18: Receiver Performance Specifications ..................................................................................... 34
Table 19: Transmitter Performance Specifications ................................................................................. 35
Rev. 5.0
3
73M1903C Data Sheet
DS_1903C_033
1 Pin Description
The 73M1903C modem Analog Front End (AFE) IC is available in a 32-pin QFN package.
SckMode
SDOUT
GPIO7
GPIO6
TYPE
SDIN
RST
26
32
31
30
29
28
27
VND
VPD
GPIO0
GPIO1
GPIO2
GPIO3
FS
SCLK
25
VPD
1
2
3
4
5
6
7
8
24
23
22
GPIO5
GPIO4
VND
FSD
VPPLL
OSCIN
OSCOUT
VNPLL
TERIDIAN
73M1903C
21
20
19
18
17
10
11
12
13
14
15
RXAP
TXAN1
TXAN2
TXAP2
TXAP1
RXAN
VPA
73M1903C QFN 32
Table 1 describes the function of each pin. There are three pairs of power supply pins, VPA (analog),
VPD (digital) and VPPLL (PLL). They should be separately decoupled from the supply source in order to
isolate digital noise from the analog circuits internal to the chip. VPPLL can be directly connected to
VPD. Failure to adequately isolate and decouple these supplies will compromise device performance.
Table 1: 32 QFN Pin Description
Pin Name
VND
VNA
VPD
VPA
VPPLL
VNPLL
Type
GND
GND
PWR
PWR
PWR
PWR
Pin #
1, 22
16
2, 25
9
20
17
Description
Negative Digital Ground.
Negative Analog Ground.
Positive Digital Supply.
Positive Analog Supply.
Positive PLL Supply, shared with VPD.
Negative PLL Ground.
Master reset. When this pin is a logic 0 all registers are
reset to their default states; Weak-pulled high-default. A
low pulse longer than 100 ns is needed to reset the
device. The device will be ready within 100 µs after this
pin goes to logic 1 state.
Crystal oscillator input. When providing an external clock
source, drive OSCIN.
Crystal oscillator circuit output pin.
Software definable digital input/output pins.
Rev. 5.0
RST
I
26
OSCIN
OSCOUT
GPIO(0-7)
4
I
O
I/O
19
18
3, 4, 5, 6, 23
24, 30, 31
VNA
16
9
DS_1903C_033
Pin Name
RXAN
RXAP
TXAN1
TXAN2
TXAP1
TXAP2
SCLK
SDOUT
SDIN
FS
TYPE
SckMode
FSD
O
Type
I
I
O
O
O
O
I/O
O
I
O
I
I
Pin #
14
15
10
11
12
13
8
32
29
7
27
28
21
Description
Receive analog negative input.
Receive analog positive input.
Transmit analog negative output 1.
Transmit analog negative output 2.
Transmit analog positive output 1.
Transmit analog positive output 2.
73M1903C Data Sheet
Serial interface clock. With master mode and SCLK
continuous selected, Freq = 256*Fs ( =2.4576 MHz for
Fs=9.6 kHz). For slave mode, this pin must be pulled
down by a resistor (<4.7
kΩ).
Serial data output (or input to the host).
Serial data input (or output from the host).
Frame synchronization. (Active Low)
Type of frame sync. 0 = late (mode0); 1 = early (mode1).
Weak-pulled high – default
Controls the SCLK behavior after FS. Open, weak-pulled
high = SCLK Continuous; tied low = 32 clocks per R/W
cycle.
Delayed frame sync to support daisy chain mode with
additional 73M1903C devices.
Rev. 5.0
5
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