CS61584A
CS61584A
Dual T1/E1 Line Interface
Dual T1/E1 Line Interface
Features
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Dual
T1/E1 Line Interface
l
3.3 Volt and 5 Volt Versions
l
Crystal-less Jitter Attenuator Meets
European CTR 12 and ETSI ETS 300 011
Specifications
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Matched Impedance Transmit Drivers
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Transmitter Tri-state Capability
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Common Transmit and
ReceiveTransformers for all Modes
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Serial and Parallel Host Mode Operation
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User-customizable Pulse Shapes
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Supports JTAG Boundary Scan
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Compliant with:
– ITU-T Recommendations: G.703, G.704,
G.706, G.732, G.775 and I.431
– American National Standards (ANSI): T1.102,
T1.105, T1.403, T1.408, and T1.231
– FCC Rules and Regulations: Part 68 and Part
15
Serial Port
Parallel Port
Hardware Mode
IPOL
IPOL (DTACK)
– AT&T Publication 62411
– ETSI ETS 300 011, 300 233, CTR 12, TBR 13
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TR-NET-00499
Description
The CS61584A is a dual line interface for T1/E1 appli-
cations, designed for high-volume cards where low
power and high density are required. The device is op-
timized for flexible microprocessor control through a
serial or parallel Host mode interface. Hardware mode
operation is also available.
Matched impedance drivers reduce power consumption
and provide substantial transmitter return loss. The
transmitter pulse shapes are customizable to allow non-
standard line loads. Crystalless jitter attenuation com-
plies with most stringent standards. Support of JTAG
boundary scan enhances system testability and
reliability.
ORDERING INFORMATION
See
page 53.
CS61584A-IQ3:3.3V, 64-pin TQFP, -40 to +85° C
CS61584A-IL5:5.0V, 68-pin PLCC, -40 to +85° C
CS61584A-IQ5:5.0V, 64-pin TQFP, -40 to +85° C
CLKE
CS
INT
SCLK
SDO
SDI
SPOL
P/S
AD3
AD4
AD5
AD6
AD7 ALE(AS)
WR(R/W)
BTS
CS
INT
RD(DS)
AD0
AD1
AD2
P/S
ATTEN0 ATTEN1 RLOOP1 RLOOP2 LLOOP TAOS1 TAOS2 CON01 CON02 CON11 CON12 CON21 CON22
CON31
CON32
CONTROL
E
N
C
O
D
E
R
D
E
C
O
D
E
R
E
N
C
O
D
E
R
D
E
C
O
D
E
R
R
E
M
O
T
E
L
O
O
P
B
A
C
K
R
E
M
O
T
E
L
O
O
P
B
A
C
K
L
O
C
A
L
L
O
C
A
L
L
O
O
P
B
A
C
K
2
L
O
C
A
L
L
O
O
P
B
A
C
K
2
TCLK1
(TDATA1) TPOS1
(AIS1) TNEG1
RCLK1
(RDATA1) RPOS1
(BPV1) RNEG1
TAOS
PULSE
SHAPING
CIRCUITRY
TTIP1
TRING1
DRIVER
JITTER
ATTENUATOR
L
O
O
P
B
A
C
K
1
L
O
C
A
L
LOS &
AIS
DETECT
CLOCK &
DATA
RECOVERY
RTIP1
RECEIVER
RRING1
TCLK2
(TDATA2) TPOS2
(AIS2) TNEG2
RCLK2
(RDATA2) RPOS2
(BPV2) RNEG2
TAOS
PULSE
SHAPING
CIRCUITRY
TTIP2
TRING2
DRIVER
JITTER
ATTENUATOR
L
O
O
P
B
A
C
K
1
LOS &
AIS
DETECT
CLOCK &
DATA
RECOVERY
RTIP2
RRING2
RECEIVER
JTAG
4
CLOCK GENERATOR
2
REFCLK
XTALOUT
1XCLK
2
2
2
3
CONTROL
RESET
MODE
TV+ TGND RV+ RGND DV+ DGND AV+ AGND BGREF PD1 PD2 LOS1 LOS2
SAD4 SAD5 SAD6 SAD7
ZTX1 ZTX2 LOS1 LOS2
Hardware Mode
Parallel Port
Serial Port
Preliminary Product Information
P.O. Box 17847, Austin,
http://www.cirrus.com
Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
©
Cirrus
Copyright
©
Cirrus Logic, Inc. 2005
Logic, Inc. 2000
(All Rights Reserved)
(All Rights Reserved)
JAN ‘01
SEP ‘05
DS261PP5
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DS261PP5
TABLE OF CONTENTS
CS61584A
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5
RECOMMENDED OPERATING CONDITIONS ....................................................................... 5
ANALOG CHARACTERISTICS ................................................................................................ 6
ANALOG CHARACTERISTICS ................................................................................................ 7
DIGITAL CHARACTERISTICS ................................................................................................. 8
SWITCHING CHARACTERISTICS .......................................................................................... 8
SWITCHING CHARACTERISTICS - SERIAL PORT ............................................................. 10
SWITCHING CHARACTERISTICS - PARALLEL PORT ........................................................ 11
SWITCHING CHARACTERISTICS - JTAG ............................................................................ 14
2. OVERVIEW ............................................................................................................................. 15
2.1 AT&T 62411 Customer Premises Application .................................................................. 16
2.2 Asynchronous Multiplexer Application ............................................................................. 16
2.3 Synchronous Application ................................................................................................. 16
3. TRANSMITTER ....................................................................................................................... 16
4. RECEIVER .............................................................................................................................. 18
5. JITTER ATTENUATOR .......................................................................................................... 19
6. REFERENCE CLOCK ............................................................................................................ 20
7. POWER-UP RESET ................................................................................................................ 20
8. LINE CONTROL AND MONITORING .................................................................................... 20
8.1 Line Code Encoder/Decoder ............................................................................................ 20
8.2 Alarm Indication Signal .................................................................................................... 20
8.3 Bipolar Violation Detection ............................................................................................... 21
8.4 Excessive Zeros Detection .............................................................................................. 21
8.5 Loss of Signal .................................................................................................................. 21
8.6 Transmit All Ones ............................................................................................................ 21
8.7 Receive All Ones ............................................................................................................. 21
8.8 Local Loopback ................................................................................................................ 22
8.9 Remote Loopback ............................................................................................................ 22
8.10 Driver Tristate ................................................................................................................ 22
8.11 Power Down ................................................................................................................... 22
8.12 Reset Pin ....................................................................................................................... 23
9. HOST MODE ........................................................................................................................... 23
9.1 Register Set ..................................................................................................................... 23
9.1.1 Status Registers .................................................................................................. 23
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including
use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the
property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained
herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts
of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other
copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic,
Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some
jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at
http://www.cirrus.com.
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CS61584A
10.
11.
12.
13.
9.1.2 Mask Registers ................................................................................................... 25
9.1.3 Control A Registers ............................................................................................. 26
9.1.4 Control B Registers ............................................................................................. 27
9.1.5 Arbitrary Waveform Registers ............................................................................. 27
9.2 Serial Port Operation ....................................................................................................... 30
9.3 Parallel Port Operation .................................................................................................... 31
JTAG BOUNDARY SCAN .................................................................................................... 31
10.1 JTAG Data Registers (DR) ............................................................................................ 32
10.2 JTAG Instructions and Instruction Register (IR) ............................................................ 33
10.3 JTAG TAP Controller ..................................................................................................... 33
10.4 Test-Logic-Reset State .................................................................................................. 33
10.5 Run-Test/Idle State ........................................................................................................ 34
10.6 Select-DR-Scan State ................................................................................................... 34
10.7 Capture-DR State .......................................................................................................... 34
10.8 Shift-DR State ................................................................................................................ 34
10.9 Exit1-DR State ............................................................................................................... 34
10.10 Pause-DR State ........................................................................................................... 35
10.11 Exit2-DR State ............................................................................................................. 35
10.12 Update-DR State ......................................................................................................... 35
10.13 Select-IR-Scan State ................................................................................................... 35
10.14 Capture-IR State .......................................................................................................... 35
10.15 Shift-IR State ............................................................................................................... 35
10.16 Exit1-IR State .............................................................................................................. 36
10.17 Pause-IR State ............................................................................................................ 36
10.18 Exit2-IR State .............................................................................................................. 36
10.19 Update-IR State ........................................................................................................... 36
10.20 JTAG Application Examples ........................................................................................ 36
PIN DESCRIPTIONS ............................................................................................................ 39
PACKAGE DIMENSIONS .................................................................................................... 46
APPLICATIONS ................................................................................................................... 48
13.1 Line Interface ................................................................................................................. 48
13.2 Power Supply ................................................................................................................ 50
13.3 Quartz Crystal Specifications ........................................................................................ 50
13.4 Crystal Oscillator Specifications .................................................................................... 50
13.5 Transformers ................................................................................................................. 51
13.6 Designing for AT&T 62411 ............................................................................................ 51
13.7 Line Protection ............................................................................................................... 51
13.8 Loop Selection Equations .............................................................................................. 51
LIST OF TABLES
Table 1. Line Configuration Selections............................................................................................. 17
Table 3. Jitter Attenuation Control.................................................................................................... 19
Table 4. CS61584A Register Set ..................................................................................................... 23
Table 5. Status Registers ................................................................................................................. 24
Table 6. Mask Registers................................................................................................................... 25
Table 7. Control A Registers ............................................................................................................ 26
Table 8. Control B Registers ............................................................................................................ 27
Table 9. Arbitrary Waveform Registers ............................................................................................ 28
Table 10. Boundary Scan Register .................................................................................................. 32
Table 11. Device Identifcation Register............................................................................................ 33
Table 12. ......................................................................................................................................... 33
DS261PP5
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CS61584A
Table 13. CS61584A External Components..................................................................................... 48
Table 14. Quartz Crystal Specifications ........................................................................................... 50
Table 15. Suggested Quartz Crystals............................................................................................... 50
Table 16. Suggested Crystal Oscillators .......................................................................................... 50
Table 17. Transformer Specifications ............................................................................................... 51
Table 18. Recommended Transformers........................................................................................... 52
LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Signal Rise And Fall Characteristics .............................................................................. 9
Recovered Clock and Data Switching Characteristics ................................................... 9
Transmit Clock and Data Switching Characteristics ...................................................... 9
Serial Port Write Timing Diagram ................................................................................. 10
Serial Port Read Timing Diagram ................................................................................ 10
Parallel Port Timing - Motorola Mode ........................................................................... 12
Parallel Port Timing - Intel Read Mode ........................................................................ 12
Parallel Port Timing - Intel Write Mode ........................................................................ 12
Parallel Port Timing - Motorola Mode to RAM .............................................................. 13
Parallel Port Timing - Intel Read Mode from RAM or ROM ......................................... 13
Parallel Port Timing - Intel Write Mode to RAM ........................................................... 13
JTAG Switching Characteristics ................................................................................... 14
Examples of CS61584A Applications ........................................................................... 15
Typical Pulse Shape at DSX-1 Cross Connect ............................................................ 17
Mask of the Pulse at the 2048 kbps Interface .............................................................. 17
Minimum Input Jitter Tolerance of Receiver (Clock Recovery Circuit and
jitter Attenuator) ............................................................................................................ 18
Typical Jitter Transfer Function .................................................................................... 19
Alarm Indication Event Relationships ........................................................................... 24
Phase Definition of Arbitrary Waveforms ..................................................................... 29
Example of Summing of Waveforms ............................................................................ 29
Serial Read/Write Format (SPOL = 0) .......................................................................... 30
Address Command byte ............................................................................................... 30
JTAG Circuitry Block Diagram ..................................................................................... 31
TAP Controller State Diagram ...................................................................................... 34
JTAG Instruction Register update ................................................................................ 37
JTAG Data Register update ......................................................................................... 38
Hardware Mode Configuration ..................................................................................... 48
Host Mode Serial Port Configuration ............................................................................ 49
Host Mode Parallel Port Configuration ......................................................................... 49
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1. CHARACTERISTICS AND SPECIFICATIONS
CS61584A
ABSOLUTE MAXIMUM RATINGS
Parameter
DC Supply (TV+1, TV+2, RV+1, RV+2, AV+, DV+) (Note 1)
Input Voltage (Any Pin)
Input Current (Any Pin)
Ambient Operating Temperature
Storage Temperature
(Note 2)
V
in
I
in
T
A
T
stg
Symbol
Min
-
RGND - 0.3
-10
-40
-65
Max
6.0
(RV+) + 0.3
10
85
150
Unit
V
V
mA
°C
°C
Notes: 1. Referenced to RGND1, RGND2, TGND1, TGND2, AGND, DGND at 0 V.
2. Transient currents of up to 100 mA will not cause SCR latch-up.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
Parameter
DC Supply (TV+1, TV+2, RV+1, RV+2, AV+, DV+) (Note 3)
3.3 V
5.0 V
Ambient Operating Temperature
Power Consumption Per Channel (3.3 V)
T1
T1
E1, 75
Ω
E1, 120
Ω
Power Consumption Per Channel (5.0 V)
T1
T1
E1, 75
Ω
E1, 120
Ω
REFCLK Frequency
T1
T1
REFCLK Frequency
E1
E1
(Note 4)
(Note 5)
(Note 6)
(Note 5)
(Note 5)
(Note 4)
(Note 5)
(Note 6)
(Note 5)
(Note 5)
1XCLK = 1
1XCLK = 0
1XCLK = 1
1XCLK = 0
T
A
P
C
-
-
-
-
P
C
-
-
-
-
(1.544 -
100 ppm)
(12.352 -
100 ppm)
(2.048 -
100 ppm)
(16.384 -
100 ppm)
350
250
320
310
1.544
12.352
2.048
16.384
-
-
-
-
(1.544 + MHz
100 ppm)
(12.352 + MHz
100 ppm)
(2.048 + MHz
100 ppm)
(16.384 + MHz
100 ppm)
310
190
250
230
-
-
-
-
mW
Symbol
Min
3.135
4.75
-40
Typ
3.3
5.0
25
Max
3.465
5.25
85
°C
mW
Unit
V
Notes: 3. TV+1, TV+2, AV+, DV+, RV+1, RV+2 should be connected together. TGND1, TGND2, RGND1, GND2,
DGND1, DGND2, DGND3 should be connected together.
4. Per channel power consumption while driving line load over operating temperature range. Includes
device and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a
50 pF capacitive load.
5. Assumes 100% ones density and maximum line length at maximum supply voltage (3.465 V or 5.25 V).
6. Assumes 50% ones density and 300 ft. line length at typical supply voltage (3.3 V or 5.0 V).
Specifications are subject to change without notice
DS261PP5
DS261F1
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