SYNCHRONOUS ETHERNET WAN PLL
and Clock Generation for IEEE-1588
Product Brief
IDT82V3398
FEATURES
HIGHLIGHTS
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Single PLL chip:
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Features 0.5 mHz to 560 Hz bandwidth
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Provides node clock for ITU-T G.8261/G.8262 Synchronous
Ethernet (SyncE)
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Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64)
jitter generation requirements
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Provides node clocks for Cellular and WLL base-station (GSM
and 3G networks)
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Provides clocks for DSL access concentrators (DSLAM), espe-
cially for Japan TCM-ISDN network timing based ADSL equip-
ments
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Provides clocks for 1 Gigabit and 10 Gigabit Ethernet application
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It supports clock generation for IEEE-1588 applications
Provides an integrated single-chip solution for Synchronous Equip-
ment Timing Source, including Stratum 3, 4E, 4, SMC, EEC-Option
1 and EEC-Option 2 Clocks
Provides SONET clocks with less than 1.5 ps of RMS Phase Jitter
(12 KHz - 20 MHz)
Supports 1 pps input and output
Employs PLL architecture to feature excellent jitter performance
and minimize the number of the external components
Supports programmable DPLL bandwidth from 0.5 mHz to 560 Hz
Supports 1.1X10
-5
ppm absolute holdover accuracy and 4.4X10
-8
ppm instantaneous holdover accuracy
Supports hitless reference switching to minimize phase transients
on the DPLL output to be no more than 0.61 ns
Supports programmable input-to-output phase offset adjustment
Limits the phase and frequency offset of the outputs
Provides OUT1~OUT6 output clocks whose frequencies cover from
1 Hz (1PPS) to 644.53125 MHz
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1PPS, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1, N x T1, N x 13.0
MHz, N x 3.84 MHz, 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz,
19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
25MHz, 25.78125 MHz, 125 MHz, 128.90625 MHz, 155.52 MHz
or 156.25 MHz or 161.1328125 MHz for CMOS outputs
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1PPS, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1, N x T1, N x 13.0
MHz, N x 3.84 MHz, 5 MHz, 10 MHz, 20 MHz, 25 MHz, E3, T3,
6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 125 MHz, 128.90625 MHz, 155.52 MHz, 156.25
MHz, 161.1328125 MHz, 311.04 MHz, 312.5 MHz, 322.265625
MHz, 622.08 MHz, 625 MHz or 644.53125 MHz for differential
Outputs
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MAIN FEATURES
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Provides IN1~IN6 input clocks whose frequencies cover from 1 Hz
(1PPS) to 625 MHz
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1PPS, 2 kHz, 4 kHz, N x 8 kHz, 1.544 MHz, 2.048 MHz, 6.25
MHz, 6.48MHz, 10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88
MHz, 51.84 MHz, 77.76 MHz, 125MHz, 155.52 MHz or 156.25
MHz for CMOS inputs
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1PPS, 2 kHz, 4 kHz, N x 8 kHz, 1.544 MHz, 2.048 MHz, 6.25
MHz, 6.48 MHz, 10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88
MHz, 51.84 MHz, 77.76 MHz, 125MHz, 155.52 MHz, 156.25
MHz, 311.04 MHz, 312.5 MHz, 622.08 MHz or 625 MHz for dif-
ferential inputs
Internal DCO can be controlled by an external processor to be used
for IEEE-1588 clock generation
Supports Forced or Automatic operating mode switch controlled by
an internal state machine. It supports Free- Run, Locked and Hold-
over modes
Supports manual and automatic selected input clock switch
Supports automatic hitless selected input clock switch on clock fail-
ure
Provides a 2 kHz, 4 kHz, 8 kHz, or 1PPS frame sync input signal,
and a 2 kHz, 8 kHz, or 1PPS frame sync output signals
Provides output clocks for BITS, GPS, 3G, GSM, etc.
Supports PECL/LVDS and CMOS input/output technologies
Supports master clock calibration
Supports Master/Slave application (two chips used together) to
enable system protection against single chip failure
Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE,
ITU-T G.812, ITU-T G.8262. ITU-T G.813 and ITU-T G.783 Recom-
mendations
I2C and Serial microprocessor interface modes
IEEE 1149.1 JTAG Boundary Scan
Single 3.3 V operation with 5 V tolerant CMOS I/Os
72-pin QFN package, Green package options available
1 Gigabit Ethernet and 10 Gigabit Ethernet
BITS / SSU
SMC / SEC (SONET / SDH)
DWDM cross-connect and transmission equipments
Synchronous Ethernet equipments
Central Office Timing Source and Distribution
Core and access IP switches / routers
Gigabit and Terabit IP switches / routers
IP and ATM core switches and access equipments
Cellular and WLL base-station node clocks
Broadband and multi-service access equipments
OTHER FEATURES
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APPLICATIONS
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1
2012 Integrated Device Technology, Inc.
August 1, 2012
DSC-7238/-
IDT82V3398 PRODUCT BRIEF
SYNCHRONOUS ETHERNET WAN PLL AND CLOCK GENERATION FOR IEEE-1588
DESCRIPTION
The IDT82V3398 is an integrated, single-chip solution for the Syn-
chronous Equipment Timing Source for Stratum 3, 4E, 4, SMC, EEC-
Option1, EEC-Option2 clocks in SONET / SDH / Synchronous Ethernet
equipment, DWDM and Wireless base station.
The device consists of a highly quality and configurable DPLL to pro-
vide system clock for node timing synchronization within a SONET /
SDH / Synchronous Ethernet network.
An input clock is automatically or manually selected for the DPLL.
The DPLL has three primary operating modes: Free-Run, Locked and
Holdover. In Free-Run mode, the DPLL refers to the master clock. In
Locked mode, the DPLL locks to the selected input clock. In Holdover
mode, the DPLL resorts to the frequency data acquired in Locked mode.
Whatever the operating mode is, the DPLL gives a stable performance
without being affected by operating conditions or silicon process varia-
tions.
There is also a high performance APLL that is used for low jitter
SONET and Ethernet Clocks
The device provides programmable DPLL bandwidths: 0.5 mHz to
560 Hz. Different settings cover all SONET / SDH clock synchronization
requirements.
A highly stable input is required for the master clock in different appli-
cations. The master clock is used as a reference clock for all the internal
circuits in the device. It can be calibrated within ±741 ppm.
All the read/write registers are accessed through a microprocessor
interface. The device supports I2C and serial microprocessor interface
modes.
In general, the device can be used in Master/Slave application. In
this application, two devices should be used together to enable system
protection against single chip failure.
Description
2
August 1, 2012
IDT82V3398 PRODUCT BRIEF
SYNCHRONOUS ETHERNET WAN PLL AND CLOCK GENERATION FOR IEEE-1588
2
Name
PIN DESCRIPTION
Pin No.
I/O
Type
Global Control Signal
OSCI
6
I
CMOS
OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
master clock for the device.
MS/SL: Master / Slave Selection
This pin, together with the MS_SL_CTRL bit (b0, 13H), controls whether the device is config-
ured as the Master or as the Slave. Refer to
Chapter 3.14 Master / Slave Configuration
for
details.
The signal level on this pin is reflected by the MASTER_SLAVE bit (b1, 09H).
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
RST: Reset
A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the device will
still be held in reset state for 500 ms (typical).
EX_SYNC1: External Sync Input 1
A 2 kHz, 4 kHz, 8 kHz, or 1PPS signal is input on this pin.
EX_SYNC2: External Sync Input 1
A 2 kHz, 4 kHz, 8 kHz, or 1PPS signal is input on this pin.
Input Clock
IN1_POS / IN1_NEG: Positive / Negative Input Clock 1
A 1PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
MHz, 10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52
MHz, 156.25 MHz, 311.04 MHz, 312.5 MHz, 622.08 MHz or 625 MHz clock is differentially
I
PECL/LVDS
input on this pair of pins. Whether the clock signal is PECL or LVDS is automatically
detected.
Single-ended input for differential input is also supported. Refer to
Chapter 9.3.2.3 Single-
Ended Input for Differential Input.
IN2_POS / IN2_NEG: Positive / Negative Input Clock 2
A 1PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
MHz, 10 MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52
MHz, 156.25 MHz, 311.04 MHz or 312.5 MHz, 622.08 MHz or 625 MHz clock is differentially
I
PECL/LVDS
input on this pair of pins. Whether the clock signal is PECL or LVDS is automatically
detected.
Single-ended input for differential input is also supported. Refer to
Chapter 9.3.2.3 Single-
Ended Input for Differential Input.
IN3: Input Clock 3
I
A 1PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
CMOS
pull-down
MHz, 10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52
MHz or 156.25 MHz clock is input on this pin.
IN4: Input Clock 4
I
A 1PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
CMOS
pull-down
MHz, 10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52
MHz or 156.25 MHz clock is input on this pin.
Description
1, 2
Table 1: Pin Description
MS/SL
71
I
pull-up
CMOS
SONET/SDH
72
I
pull-down
CMOS
RST
55
I
pull-up
CMOS
Frame Synchronization Input Signal
EX_SYNC1
EX_SYNC2
33
38
I
pull-down
I
pull-down
CMOS
CMOS
IN1_POS
IN1_NEG
29
30
IN2_POS
IN2_NEG
31
32
IN3
34
IN4
35
Pin Description
5
August 1, 2012
NXP MCU
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