19-3818; Rev 0; 9/05
KIT
ATION
EVALU
BLE
AVAILA
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
General Description
Features
♦
DC-Coupled Clock Phase Aligner for Burst-Mode
GPON Applications
♦
13-Bit Burst Acquisition Time
♦
0.85UI High-Frequency Jitter Tolerance
♦
Continuous Clock Output
♦
Byte Rate (1/8th Data Rate) Reference Clock Input
♦
Lock Detect Output
♦
LVPECL Serial Data Input and Output
♦
LVPECL Reset Input
MAX3634
The MAX3634 burst-mode clock phase aligner (CPA) is
designed specifically for 622Mbps or 1244Mbps GPON
(ITU G.984) optical line terminal (OLT) receiver applica-
tions. The MAX3634 provides clock and clock-aligned
resynchronized upstream data through differential
LVPECL outputs. Using the OLT system clock as a ref-
erence, the MAX3634 aligns to the input data and
acquires within the first 13 bits of the burst. The CPA
operates with received data that is frequency locked to
the OLT reference. The acquisition time, bit-error ratio,
and jitter tolerance all support GPON PMD specifica-
tions. LVPECL high-speed clock and data outputs pro-
vide compatibility with FPGAs at 622Mbps and with the
MAX3885 deserializer at 1244Mbps.
The MAX3634 is available in a low-profile, 7mm x 7mm,
48-lead TQFN package. The MAX3634 operates from a
single +3.3V supply, over the -40°C to +85°C tempera-
ture range.
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
PIN-
PACKAGE
48 TQFN
(7mm x 7mm)
PKG
CODE
T4877-6
Applications
622Mbps GPON OLT Receivers
1244Mbps GPON OLT Receivers
MAX3634ETM
Pin Configuration appears at end of data sheet.
Typical Application Circuit
BURST RESET
BURST ENABLE
DATA
4
DATA
CLOCK
MAX3634
CLOCK
BURST-MODE
CLOCK PHASE
ALIGNER
BURST-MODE
TIA/LA
UPSTREAM
1244Mbps
MAX3656
BURST-MODE
LASER DRIVER
MAX3892
DATA
SERIALIZER
DIVIDE BY 16
DIVIDE BY 8
OLT CLOCK
DATA
RATESEL
MAX3738
CONTINUOUS
LASER DRIVER
DOWNSTREAM
2488Mbps
MAX3864
MAX3748A
TIA/LA
MAX3872
SONET
CDR
CLOCK
DATA
GPON OPTICAL LINE TERMINATION
GPON OPTICAL NETWORK TERMINATION
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
MAX3634
ABSOLUTE MAXIMUM RATINGS
V
CC
, V
CC
I, V
CC
O, V
CC
V ........................................-0.5V to +4.0V
SDI±, RST±,
REFCLK±,
RATESEL, FILT, TEST.............................-0.5V to (V
CC
+ 0.5V)
LVPECL Output Current (SDO±, SCLK±, LOCK±).............50mA
Continuous Power Dissipation (T
A
= +85°C)
48-Lead TQFN package
(derate 27.8mW/°C above +85°C) .............................1800mW
Storage Temperature Range .............................-55°C to +150°C
Operating Ambient Temperature Range .............-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+400°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
Supply Current
Data Rate
Reference Clock Input Frequency
SDI, RST, REFCLK Differential
Input
SDI±, RST±, REFCLK± Input
Current
RST Input Rise/Fall Times
SDI±, RST±, REFCLK± Common-
Mode Input
T
A
= 0°C to +85°C (Note 1)
V
OL
T
A
= -40°C to 0°C (Note 1)
T
A
= 0°C to +85°C (Note 1)
V
OH
T
A
= -40°C to 0°C (Note 1)
Jitter Tolerance
Acquisition Time
Bit-Error Ratio
SDO±, LOCK± Transition Time
SCLK± Transition Time
t
r
, t
f
t
r
, t
f
622Mbps (Notes 2, 5, 6)
1244Mbps (Notes 2, 5, 6)
(Notes 2, 3)
After acquisition (Notes 2, 4)
20% to 80% (Note 1)
20% to 80% (Note 1)
t
r
, t
f
Rate = 1244Mbps
Rate = 622Mbps
V
CC
- 1.49
V
CC
- 1.81
V
CC
- 1.83
V
CC
- 1.025
V
CC
- 1.085
0.73
0.73
0.83
0.81
13
10
-10
SYMBOL
I
CC
CONDITIONS
Not including LVPECL output current
RATESEL = low
RATESEL = high
RATESEL = low
RATESEL = high
MIN
TYP
315
1244.16
622.08
155.52
77.76
MAX
390
UNITS
mA
Mbps
MHz
V
IN
200
-180
1600
+180
200
200
V
CC
- V
IN
/4
V
CC
- 1.62
mV
P-P
µA
ps
V
SDO±, SCLK±, LOCK± Output
Voltage Low
V
V
CC
- 1.555
V
CC
- 0.88
V
V
CC
- 0.88
UI
P-P
Bits
ps
ps
SDO±, SCLK±, LOCK± Output
Voltage High
265
200
2
_______________________________________________________________________________________
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
Serial Data Output Clock-to-Q
Delay (Figure 1)
Serial Data Output Q-to-Clock
Delay (Figure 1)
RATESEL Input High
RATESEL Input Low
RATESEL Input Current
SYMBOL
t
CLK-Q
t
Q-CLK
V
IH
V
IL
V
IN
= 0V or V
CC
-100
CONDITIONS
622Mbps (Notes 1, 2)
1244Mbps (Notes 1, 2)
622Mbps (Notes 1, 2)
1244Mbps (Notes 1, 2)
MIN
500
250
500
250
2
0.8
+100
TYP
MAX
UNITS
ps
ps
V
V
µA
MAX3634
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
PECL output must have external termination of 50Ω to V
CC
- 2V (Thevenin equivalent).
AC parameters are guaranteed by design and characterization.
From start of PON burst, 101010101010 preamble sequence.
BER, acquisition time requirements are met with 100mV
P-P
sinusoidal noise on V
CC
, 0 < f
NOISE
≤
10MHz.
Measured with 20ps
RMS
input random jitter (1.244Mbps), 30ps
RMS
(622Mbps)
Jitter tolerance refers to the variation in phase between REFCLK and SDI after acquisition.
(SCLK+) - (SCLK-)
(SDO+) - (SDO-)
t
CLK-Q
t
Q-CLK
Figure 1. Definition of Clock-to-Q and Q-to-Clock Delay
Typical Operating Characteristics
(V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted)
1.244Gbps
INPUT AND OUTPUT EYE DIAGRAMS
MAX3634 toc01
622Mbps
INPUT AND OUTPUT EYE DIAGRAMS
MAX3634 toc02
BURST CAPTURE AT 1.244Gbps
RST
MAX3634 toc03
SDI
SDI
SDI
LOCK
SDO
SDO
SDO
200ps/div
400ps/div
1ns/div
_______________________________________________________________________________________
3
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
MAX3634
Typical Operating Characteristics (continued)
(V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted)
JITTER TOLERANCE vs. SDI-TO-REFCLK
PHASE (1.244Gbps)
MAX3634 toc04
JITTER TOLERANCE vs. SDI-TO-REFCLK
PHASE (622Mbps)
MAX3634 toc05
SUPPLY CURRENT
vs. TEMPERATURE
MAX3634 toc06
1.0
0.9
JITTER TOLERANCE (UI
P-P
)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
200
400
600
LIMITED BY TEST EQUIPMENT
1.0
0.9
JITTER TOLERANCE (UI
P-P
)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
LIMITED BY TEST EQUIPMENT
340
320
SUPPLY CURRENT (mA)
300
280
260
240
220
EXCLUDES PECL OUTPUT CURRENT
200
800
0
200
400
600
800
-50
0
50
100
SDI-TO-REFCLK PHASE (ps)
SDI-TO-REFCLK PHASE (ps)
AMBIENT TEMPERATURE (°C)
Pin Description
PIN
1, 2, 12, 25, 36, 37, 48
3, 6, 7, 10
4
5
8
9
11, 38, 39, 44, 47
13–20, 22, 23
21, 24, 26, 29, 32, 35
27
28
30
31
33
34
40
41, 43
42
45
46
EP
NAME
GND
V
CC
I
SDI+
SDI-
RST+
RST-
V
CC
TEST
V
CC
O
LOCK-
LOCK+
SDO-
SDO+
SCLK-
SCLK+
RATESEL
V
CC
V
FILT
REFCLK-
REFCLK+
Supply Ground
+3.3V Supply for Input Buffers
Positive Serial Data Input, LVPECL
Negative Serial Data Input, LVPECL
Positive Reset Input, LVPECL. Reset (= RST+ - RST-) is falling edge triggered.
Negative Reset Input, LVPECL
+3.3V Supply for Digital Circuitry
Production Test Pins, Reserved. Leave open for normal operation.
+3.3V Supply for Output Buffers
Negative Lock Status Output, LVPECL
Positive Lock Status Output, LVPECL. Lock (=
(LOCK+)
- (LOCK-)) high indicates that the
MAX3634 has acquired the correct phase.
Negative Serial Data Output, LVPECL
Positive Serial Data Output, LVPECL
Negative Serial Clock Output, LVPECL
Positive Serial Clock Output, LVPECL
Rate Select Input, TTL. High selects 622.08Mbps operation.
+3.3V Supply for VCO
PLL Filter Capacitor. Connect a 0.1µF X7R capacitor from pin 42 to V
CC
V.
Negative Reference Clock Input, LVPECL (1/8th data rate)
Positive Reference Clock Input, LVPECL
FUNCTION
Exposed Pad The exposed pad must be connected to the ground plane for proper thermal performance.
4
_______________________________________________________________________________________
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
General Description
Theory of Operation
The MAX3634 CPA provides serial clock and data out-
puts for GPON upstream bursts.
The burst-mode CPA operates on the principle that the
recovered clock from the ONT CDR is used at each
ONT to clock upstream data bursts out of the ONT con-
troller. The burst-mode CPA has logic that determines
the correct phase relationship between the upstream
data and the OLT reference clock at the beginning of
each ONT’s burst, and resamples the upstream data at
each bit using that clock.
The burst-mode CPA contains a phase-locked loop
(PLL) that synchronizes its oscillator to the reference
clock input. This oscillator drives a phase splitter, which
generates eight evenly spaced phases of the serial
clock, which are used to sample the input data at 1/8th
bit intervals in eight flip-flops. Combinatorial and
sequential logic measures the preamble, and based on
the phase of the preamble, determines which one of
the eight clock phases is at the center of the input data
bits. The data from the flip-flop associated with this
phase is then steered through a multiplexer to the CPA
output, which requires four or five additional clock peri-
ods until valid data is output. The CPA serial output
clock is continuous, without any phase jumps or dis-
continuities from burst to burst.
The burst-mode CPA requires a preamble sequence of
1010101010101 (13 bits) for correct phase alignment.
Typically, output begins after the 12th bit, although for
certain data/phase relationships, 13 bits are required.
An LVPECL-compatible lock status output is provided,
which indicates when the correct phase has been
acquired and valid serial output data is available. This
output remains low until reset by the burst reset input
(RST). The output data is disabled (held low) during the
period between reset and lock.
MAX3634
Reference Clock Input
The MAX3634 includes a PLL, which multiplies the ref-
erence clock by eight for use in the retiming circuitry.
For correct operation, the REFCLK input must be con-
nected to the OLT byte-rate reference clock, which
must be equal to 1/8th the serial data rate, and must
have a 40% to 60% duty cycle. This must be the same
clock source used to time the downstream data, and
the upstream data must be frequency locked to this
source.
The RATESEL input is used to configure 622Mbps or
1244Mbps operation; when RATESEL is high, the
MAX3634 operates at 622Mbps.
REFCLK+
REFCLK-
LVPECL
622Mbps/1244Mbps
PLL/PHASE SPLITTER
φ0
RATESEL
TTL
φ7
D
Q
SYNCHRONIZER
MUX
SDI+
SDI-
LVPECL
D
Q
LVPECL
MAX3634
BURST-MODE CPA
SDO+
SDO-
SCLK+
LVPECL
SCLK-
D
Q
RST+
RST-
LVPECL
PHASE-ACQUISITION LOGIC
LVPECL
LOCK+
LOCK-
Figure 2. Functional Block Diagram
_______________________________________________________________________________________
5
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