CY22381
CY223811
Three-PLL General Purpose FLASH
Programmable Clock Generator
Features
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Improves frequency accuracy over temperature, age, process,
and initial offset
Non-volatile programming enables easy customization,
ultra-fast turnaround, performance tweaking, design timing
margin testing, inventory control, lower part count, and more
secure product supply. Can also be programmed multiple times
which reduces programming errors and provides an easy
upgrade path for existing designs
In-house programming of samples and prototype quantities is
available using the CY3672 FTG development Kit. Production
quantities are available through Cypress’s value-added
distribution partners or by using third party programmers from
BP Microsystems, HiLo Systems, and others.
Performance suitable for high-end multimedia,
communications, industrial, A/D converters, and consumer
applications
Supports numerous low-power application schemes and
reduces EMI by allowing unused outputs to be turned off
Adjust crystal drive strength for compatibility with virtually all
crystals
External frequency select option for PLL1, CLKA, and CLKB
Industry standard supply voltage
Industry standard packaging saves on board space
Easy-to-use software support for design entry
Three integrated phase-locked loops
Ultra-wide divide counters (eight-bit Q, eleven-bit P, and
seven-bit post divide)
Improved linear crystal load capacitors
Flash programmability
Field programmability
Low-jitter, high-accuracy outputs
Power-management options (Shutdown, OE, Suspend)
Configurable crystal drive strength
Frequency select option through external LVTTL Input
3.3V operation
8-pin SOIC package (CY22381)
8-pin SOIC package with NiPdAu lead finish (CY223811)
CyClocks RT™ support
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Benefits
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Generates up to three unique frequencies on three outputs up
to 200 MHz from an external source. Functional upgrade for
current CY2081 family.
Allows for 0 ppm frequency generation and frequency
conversion under the most demanding applications
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Logic Block Diagram
XTALIN
XTALOUT
OSC.
PLL1
CONFIGURATION
FLASH
11-BIT P
8-BIT Q
Divider
7-BIT
CLKC
PLL2
SHUTDOWN/OE
FS/SUSPEND
11-BIT P
8-BIT Q
4×3
Crosspoint
Switch
Divider
7-BIT
CLKB
PLL3
11-BIT P
8-BIT Q
Divider
7-BIT
CLKA
Cypress Semiconductor Corporation
Document #: 38-07012 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 11, 2008
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CY22381
CY223811
Pinouts
Figure 1. CY22381, CY223811- 8-pin SOIC
CLKC
GND
XTALIN
XTALOUT
1
2
3
4
8
7
6
5
FS/
SUSPEND
/OE/
SHUTDOWN
V
DD
CLKA
CLKB
Pin Definitions
Name
CLKC
GND
XTALIN
XTALOUT
CLKB
CLKA
V
DD
FS/SUSPEND/
OE/SHUTDOWN
Pin Number
1
2
3
4
5
6
7
8
Description
Configurable clock output C
Ground
Reference crystal input or external reference clock input
Reference crystal feedback (float if XTALIN is driven by external reference clock)
Configurable clock output B
Configurable clock output A
Power supply
General Purpose Input. Can be Frequency Control, Suspend mode control, Output
Enable, or full-chip shutdown.
of PLL1, the output divider of CLKB, and the output divider of
CLKA. Any divider change as a result of switching the FS input
is guaranteed to be glitch free.
The general-purpose input can simultaneously control the
Suspend feature, turning off a set of PLLs and outputs
determined during programming.
When programmed as an Output Enable (OE) the input forces
all outputs to be placed in a three-state condition when LOW.
When programmed as a Shutdown, the input forces a full chip
shutdown mode when LOW.
Operation
The CY22381 is an upgrade to the existing CY2081. The new
device has a wider frequency range, greater flexibility, improved
performance, and incorporates many features that reduce PLL
sensitivity to external system issues.
The device has three PLLs that allow each output to operate at
an independent frequencies. These three PLLs are completely
programmable.
The CY223811 is the CY22381 with NiPdAu lead finish.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to the crosspoint switch. The frequency of PLL1 can optionally
be changed by using the external CMOS general purpose input.
See the following section on “General-Purpose Input” for more
detail.
PLL2 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the crosspoint switch.
PLL3 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross-point switch.
Crystal Input
The input crystal oscillator is an important feature of this device
because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, processes, performances, and qualities.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and temperature
changes. Non-linear (FET gate) crystal load capacitors must not
be used for MPEG, POTS dial tone, communications, or other
applications that are sensitive to absolute frequency
requirements
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with a
resolution of 0.375pF for a total crystal load range of 6pF to 30pF.
For driven clock inputs the input load capacitors may be
completely bypassed. This enables the clock chip to accept
driven frequency inputs up to 166 MHz. If the application requires
a driven input, then XTALOUT must be left floating.
General-Purpose Input
The CY22381 features an output control pin (pin 8) that can be
programmed to control one of four features.
When programmed as a Frequency Select (FS), the input can
select between two arbitrarily programmed frequency settings.
The Frequency Select can change the following; the frequency
Document #: 38-07012 Rev. *F
Page 2 of 9
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CY22381
CY223811
5
μA
(typical). After leaving shutdown mode, the PLLs has to
relock.
When configured as SUSPEND, the general-purpose input can
be configured to shut down a customizable set of outputs and/or
PLLs, when LOW. All PLLs and any of the outputs can be shut
off in nearly any combination. The only limitation is that if a PLL
is shut off, all outputs derived from it must also be shut off.
Suspending a PLL shuts off all associated logic, while
suspending an output forces a three-state condition.
Output Configuration
Under normal operation there are four internal frequency
sources that may be routed through a programmable crosspoint
switch to any of the three outputs through programmable
seven-bit output dividers. The four sources are: reference, PLL1,
PLL2, and PLL3. The following is a description of each output.
CLKA’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one of two programmable
registers controlled by FS.
CLKB’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one of two programmable
registers controlled by FS.
CLKC’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one programmable register.
The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15pF. While driving
multiple loads is possible with the proper termination, it is
generally not recommended.
Improving Jitter
Jitter Optimization Control is useful in mitigating problems
related to similar clocks switching at the same moment and
causing excess jitter. If one PLL is driving more than one output,
the negative phase of the PLL can be selected for one of the
outputs. This prevents the output edges from aligning, allowing
superior jitter performance.
CyClocks RT Software
CyClocks RT is our second-generation application that allows
users to configure this device. The easy-to-use interface offers
complete control of the many features of this family including
input frequency, PLL and output frequencies, and different
functional options. Data sheet frequency range limitations are
checked and performance tuning is automatically applied. You
can download a free copy of CyClocks RT on Cypress’s web site
at
http://www.cypress.com.
Power-Saving Features
When configured as OE, the general-purpose input three-states
all outputs when pulled LOW. When configured as Shutdown, a
LOW on this pin three-states all outputs and shuts off the PLLs,
counters, the reference oscillator, and all other active
components. The resulting current on the V
DD
pins is less than
Document #: 38-07012 Rev. *F
Page 3 of 9
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CY22381
CY223811
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply Voltage................................................–0.5V to +7.0V
DC Input Voltage ..............................–0.5V to + (V
DD
+ 0.5V)
Storage Temperature .................................. –65°C to +125°C
Junction Temperature .................................................. 125°C
Data Retention at Tj = 125°C ................................> 10 years
Maximum Programming Cycles........................................100
Package Power Dissipation...................................... 250 mW
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ...........................
≥
2000V
Latch up (per JEDEC 17) ....................................
≥
±200 mA
Operating Conditions
Parameter
V
DD
T
A
Supply Voltage
Commercial Operating Temperature, Ambient
Industrial Operating Temperature, Ambient
C
LOAD_OUT
Max. Load Capacitance
f
REF
External Reference Crystal
External Reference Clock
[2]
, Commercial
External Reference Clock
[2]
, Industrial
t
PU
Power up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)
Description
Min
3.135
0
–40
–
8
1
1
0.05
Typ
3.3
–
–
–
–
–
–
–
Max
3.465
+70
+85
15
30
166
150
500
Unit
V
°C
°C
pF
MHz
MHz
MHz
ms
Electrical Characteristics
Parameter
I
OH
I
OL
C
XTAL_MIN
C
XTAL_MAX
C
IN
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
I
DDS
Description
Output High Current
[3]
Output Low Current
[3]
Crystal Load Capacitance
[3]
Crystal Load Capacitance
[3]
Input Pin Capacitance
[3]
HIGH-level Input Voltage
LOW-level Input Voltage
Input HIGH Current
Input LOW Current
Output Leakage Current
Total Power Supply Current
Conditions
[1]
V
OH
= V
DD
– 0.5, V
DD
= 3.3 V
V
OL
= 0.5V, V
DD
= 3.3 V
Capload at minimum setting
Capload at maximum setting
Except crystal pins
CMOS levels,% of V
DD
CMOS levels,% of V
DD
V
IN
= V
DD
– 0.3 V
V
IN
= +0.3 V
Three-state outputs
3.3 V Power Supply; 3 outputs at 50 MHz
3.3 V Power Supply; 3 outputs at 166 MHz
Total Power Supply Current in Shutdown active
Shutdown Mode
Min
12
12
–
–
–
70%
–
–
–
–
–
–
–
Typ
24
24
6
30
7
–
–
<1
<1
–
35
70
5
Max
–
–
–
–
–
–
30%
10
10
10
–
–
20
Unit
mA
mA
pF
pF
pF
V
DD
V
DD
μA
μA
μA
mA
mA
μA
Notes
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2. External input reference clock must have a duty cycle between 40% and 60%, measured at V
DD
/2.
3. Guaranteed by design, not 100% tested.
Document #: 38-07012 Rev. *F
Page 4 of 9
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CY22381
CY223811
Switching Characteristics
Parameter
1/t
1
t
2
Name
Output Frequency
[3, 4]
Output Duty Cycle
[3, 5]
Description
Clock output limit, Commercial
Clock output limit, Industrial
Duty cycle for outputs, defined as t
2
÷
t
1
,
Fout < 100 MHz, divider >= 2, measured
at V
DD
/2
Duty cycle for outputs, defined as t
2
÷
t
1
,
Fout > 100 MHz or divider = 1, measured
at V
DD
/2
t
3
t
4
t
5
Rising Edge Slew Rate
[3]
Falling Edge Slew Rate
[3]
Output Three-state Timing
[3]
Output clock rise time, 20% to 80% of V
DD
Output clock fall time, 20% to 80% of V
DD
Time for output to enter or leave
three-state mode after SHUTDOWN/OE
switches
Peak-to-peak period jitter, CLK outputs
measured at V
DD
/2
PLL Lock Time from Power up
Min
–
–
45%
Typ.
–
–
50%
Max
200
166
55%
Unit
MHz
MHz
40%
50%
60%
0.75
0.75
–
1.4
1.4
150
–
–
300
V/ns
V/ns
ns
t
6
t
7
Clock Jitter
[3, 6]
Lock Time
[3]
–
–
200
1.0
–
3
ps
ms
Switching Waveforms
Figure 2. All Outputs, Duty Cycle and Rise and Fall Time
t
1
t
2
OUTPUT
t
3
t
4
Figure 3. Output Three-State Timing
OE
t
5
ALL
THREE-STATE
OUTPUTS
t
5
Figure 4. CLK Output Jitter
t
6
CLK
OUTPUT
Notes
4. Guaranteed to meet 20% – 80% output thresholds and duty cycle specifications.
5. Reference Output duty cycle depends on XTALIN duty cycle.
6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
Document #: 38-07012 Rev. *F
Page 5 of 9
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