MIC59P50
8-Bit Parallel-Input Protected
Latched Driver
General Description
The MIC59P50 parallel-input latched driver is a high-
voltage (80V), high-current (500mA) integrated circuit
comprised of eight CMOS data latches, a bipolar
Darlington transistor driver for each latch, and CMOS
control circuitry for the common CLEAR, STROBE, and
OUTPUT ENABLE functions. Similar to the MIC5801,
additional protection circuitry supplied on this device
includes thermal shutdown, undervoltage lockout (UVLO),
and overcurrent shutdown.
The bipolar/MOS combination provides an extremely low-
power latch with maximum interface flexibility. The
MIC59P50 has open-collector outputs capable of sinking
500mA and integral diodes for inductive load transient
suppression with a minimum output breakdown voltage
rating of 80V above V
EE
(50V sustaining). The drivers can
be operated with a split supply, where the negative supply
is down to –20V and may be paralleled for higher load
current capability.
With a 5V logic supply, the MIC59P50 will typically operate
at better than 5MHz. With a 12V logic supply, significantly
higher speeds are obtained. The CMOS inputs are
compatible with standard CMOS, PMOS, and NMOS
circuits. TTL circuits may require pull-up resistors.
Each of these eight outputs has an independent
overcurrent shutdown at 500mA. Upon current shutdown,
the affected channel will turn OFF and the flag will go low
until V
DD
is cycled or the /ENABLE/RESET pin is pulsed
high. Current pulses less than 2µs will not activate
overcurrent shutdown. Temperatures above +165°C will
shut down the device and activate the open-collector
FLAG output at pin 1. The UVLO circuit disables the
outputs at low V
DD
; hysteresis of 0.5V is provided.
Datasheets and support documentation are available on
Micrel’s website at:
www.micrel.com.
Features
•
•
•
•
•
•
•
•
•
•
4.4MHz minimum data input rate
High-voltage, high-current outputs
Per-output overcurrent shutdown (500mA typical)
Undervoltage lockout
Output fault flag
Output transient protection diodes
CMOS, PMOS, NMOS, and TTL-compatible inputs
Internal pull-down resistors
Low-power CMOS latches
Single or split supply operation
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
July 29, 2015
Revision 2.0
Micrel, Inc.
MIC59P50
Functional Diagram
July 29, 2015
2
Revision 2.0
Micrel, Inc.
MIC59P50
Ordering Information
Part Number
MIC59P50YN
MIC59P50YV
MIC59P50YWM
Note:
1. 300mm “Skinny DIP”
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package
24-Pin Plastic DIP
28-Pin PLCC
24-Pin Wide SOIC
(1)
Pb-Free
√
√
√
Pin Configuration
24-Pin PDIP (N)
24-Pin Wide SOIC (WM)
(Top View)
28-Pin PLCC (V)
(Top View)
Pin Description
Pin Number
PDIP & SOIC
1
2
3
4-11
12
13
14-21
22
23
24
Pin Number
PLCC
2
3
4
5-12
15
17
18-25
26
27
28
Pin Name
Pin Name
Error flag. Open-collector output is low upon overcurrent fault or
overtemperature fault. /OE/RESET must be pulled high to reset the flag and
fault condition.
Sets all latches to OFF (open).
Input strobe pin. Loads output latches when high.
Parallel inputs, 1 through 8.
Output ground (substrate). Most negative voltage in the system connects here.
Transient suppression diodes cathode common pin.
Parallel outputs, 8 through 1.
Logic positive supply voltage.
Output enable reset. When low, outputs are active. When high, outputs are
inactive and the flag and outputs are reset from a fault condition. An
undervoltage condition emulates a high /OE input.
Logic reference (ground) pin.
/FLAG
CLEAR
STROBE
IN
n
VEE
COMMON
OUT
n
VDD
/OE/RESET
VSS
July 29, 2015
3
Revision 2.0
Micrel, Inc.
MIC59P50
Absolute Maximum Ratings
(2)
Input Voltage (V
CE
) ....................................................... +80V
Supply Voltage
(V
DD
) ......................................................................... 15V
(V
DD
– V
EE
) ............................................................... 25V
Continuous Collector Current (I
C
) .............................. 500mA
(4)
Protected Current ....................................................... 1.5A
Lead Temperature (soldering, 10s) ............................ 260°C
Storage Temperature (Ts)......................... –65°C to +150°C
(5)
ESD Rating ................................................. ESD Sensitive
Operating Ratings
(3)
Input Voltage (V
IN
) .................................. –0.3V to V
DD
+0.3V
Operating Temperature (T
A
)........................ –40°C to +85°C
Junction Temperature (T
J
) ....................................... +150°C
Power Dissipation (P
D
)
Plastic DIP (N) ....................................................... 2.4W
Derate above T
A
= +25°C ............................ 24mW/°C
PLCC (V) ............................................................... 1.6W
Derate above T
A
= +25°C ............................ 16mW/°C
Wide SOIC (WM) ................................................... 1.4W
Derate above T
A
= +25°C ............................ 14mW/°C
Electrical Characteristics
(6)
V
DD
= 5V; T
A
= 25°C, unless noted.
Symbol
I
CEX
V
CE(SAT)
Parameter
Output Leakage Current
Collector-Emitter
Saturation Voltage
V
IN(0)
Input Voltage
V
DD
= 12V
V
DD
= 10V
V
DD
= 5V,
Note 7
V
DD
= 12V
R
IN
Input Resistance
V
DD
= 10V
V
DD
= 5V
I
OL
I
OH
Notes:
2. Exceeding the absolute maximum ratings may damage the device.
3. The device is not guaranteed to function outside its operating ratings.
4. Each channel VEE connection must be designed to minimize inductance and resistance.
5. Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5kΩ in series with 100pF.
6. Specification for packaged product only.
7. Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic “1”.
Condition
V
CE
= 80V, T
A
= +25°C
V
CE
= 80V, T
A
= +70°C
I
C
= 100mA
I
C
= 200mA
I
C
= 350mA
Min.
Typ.
Max.
50
100
Units
µA
µA
V
V
V
V
V
V
V
0.9
1.1
1.3
1.1
1.3
1.6
1.0
10.5
8.5
3.5
50
50
50
200
300
600
15
50
V
IN(1)
kΩ
kΩ
kΩ
mA
nA
/Flag Output Current
/Flag Output Leakage
V
OL
= 0.4V
V
OH
= 12V
July 29, 2015
4
Revision 2.0
Micrel, Inc.
MIC59P50
Electrical Characteristics
(6)
(Continued)
V
DD
= 5V; T
A
= 25°C, unless noted.
Symbol
I
DD(ON)1
Parameter
Supply Current
One Output Active
Condition
V
DD
= 12V, outputs open
V
DD
= 10V, outputs open
V
DD
= 5V, outputs open
V
DD
= 12V, outputs open
I
DD(ON) All
Supply Current
All Outputs Active
V
DD
= 10V, outputs open
V
DD
= 5V, outputs open
V
DD
= 12V, outputs open, inputs = 0V
I
DD(OFF)
Supply Current OFF
V
DD
= 5V, outputs open, inputs = 0V
I
R
I
LIM
V
SU
V
DD MIN
V
F
Clamp Diode Leakage Current
Overcurrent Threshold
Start-up Voltage
Minimum Operating V
DD
Clamp Diode Forward Voltage
Thermal Shutdown
Thermal Shutdown Hysteresis
Notes:
8. Undervoltage lockout is guaranteed to release device at no more than 4.5V and disable the device at no less than 3.0V input logic voltage.
Min.
Typ.
3.3
3.1
2.4
6.4
6.0
4.7
3.0
2.2
Max.
4.5
4.5
3.6
10.0
9.0
7.5
4.5
3.6
50
100
Units
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
mA
V
R
= 80V, T
A
= +25°C
V
R
= 80V, T
A
= +70°C
Each output
Note 8
3.5
3.0
I
F
= 350mA
500
4.0
3.5
1.7
165
10
4.5
4.0
2.0
V
V
V
°C
Truth Table
IN
n
0
1
X
X
X
X
Note:
X = Irrelevant
t-1 = Previous output state
t = Present output state
Strobe
1
1
X
X
0
0
Clear
0
0
1
X
0
0
Output Enable
0
0
X
1
0
0
OUT
n
t-1
X
X
X
X
ON
OFF
t
OFF
ON
OFF
OFF
ON
OFF
Information present at an input is transferred to its latch when the STROBE is high. A high CLEAR input will set all latches
to the output OFF condition regardless of the data or STROBE input levels. A high OUTPUT ENABLE will set all outputs
to the OFF condition, regardless of any other input conditions. When the OUTPUT ENABLE is low, the outputs depend on
the state of their respective latches. If current shutdown is activated, the OUTPUT ENABLE must be pulsed high to
restore operation and reset the FLAG. Overtemperature faults are not latched and require no reset pulse.
July 29, 2015
5
Revision 2.0
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