TSOT0410G4,TSOT0410G4 pdf中文资料,TSOT0410G4引脚图,TSOT0410G4电路-Datasheet-电子工程世界

Datasheet> 器件分类 > TSOT0410G4

文档预览

TSOT0410G4: 产品描述SONET/SDH STS-192 Overhead and Path Processor; 文件大小1MB，共190页; 制造商Agere System(LSI Logic)

下载文档全文预览

TSOT0410G4概述

SONET/SDH STS-192 Overhead and Path Processor

文档预览

下载PDF文档

全文
预览

Data Sheet

May 2003

TSOT0410G4 SONET/SDH

STS-192 Overhead and Path Processor

Features

General

Extracts and outputs, on a serial link, all transport

overhead bytes in the receive data and inserts any,

or all, transport overhead bytes in the transmit data

using a corresponding serial input.

Extracts and outputs, on serial links, the section

user channel (F1), orderwire channels (E1, E2),

and data communication channels (D1—D3 and

D4—D12) for the receive data. Inserts correspond-

ing serial input signals into the transmit data.

Extracts, integrates, and stores the automatic pro-

tection switch (APS) channel bytes (K1, K2) for the

receive data and detects protection switch failure

alarms. Inserts APS bytes in the transmit data from

internal registers or from add data overhead bytes.

Detects line alarm indication signal (AIS) and

remote defect indication (RDI) based on the K2

byte of the receive data. Inserts line AIS and RDI in

the transmit data. Optionally inserts line RDI auto-

matically due to LOS, LOF, or line AIS defects.

Extracts, integrates, and stores the synchronization

status byte (S1) for the receive data. Inserts the

synchronization status byte into the transmit data

from an internal register or from a value encoded on

the transmit frame synchronous input.

Calculates, detects, and counts section and line

BIP-8 errors (B1, B2) for the receive data, and

inserts BIP-8 in the transmit data. Supports either

bit or block error accumulation of B1 errors (sepa-

rately provisionable), and bit error accumulation of

B2 errors.

Extracts and counts line remote errors (REI) for the

receive data (M1), and inserts REI in the transmit

data based on B2 errors.

SS bit mode supports SONET (00) or SDH (10) val-

ues and defines the value of the SS bits for

unequipped signal insertion. In normal mode,

SS bits can be passed through or overwritten with a

provisioned value. All SS bit provisioning is done at

a STM-16 level affecting all AU-3s.

The B1 error mask can be extracted serially on the

ROHDAT interface, and the B2 error mask can be

extracted serially on the local orderwire, express

orderwire, and orderwire clock pins.

Section overhead (RSOH) and line overhead

(MSOH) termination, and path overhead monitoring

for one SONET STS-192 (SDH STM-64) or four

STS-48 (STM-16) signals.

Supports any valid combination of STS-1 and

concatenated payloads from STS-3c to STS-192c.

Microprocessor interface configurable to operate

with most commercial microprocessors.

IEEE

1149.1 port with memory built-in self-test

(BIST), scan, and boundary scan (JTAG).

Low-power 2.5 V operation with 3.3 V (5 V tolerant)

inputs and outputs.

EIA

-644,

IEEE

1596.3 compliant LVDS buffers*.

600-pin LBGA package.

–40 °C to +85 °C temperature range.

STS-192/STM-64 (Line Interface)

Provides a 16-bit (or 4

4-bit) wide, 622 MHz differ-

ential line interface.

Synchronizes to the receive data frames and

detects severely errored framing (SEF) and loss of

frame (LOF). Also inserts the framing bytes (A1 and

A2) in the transmit data.

Supports enhanced framing (A1, A1, A2, A2).

Performs frame-synchronous scrambling and

descrambling of the STS-192/STS-48 data, and

loss of signal (LOS) is detected.

Extracts the 64-byte or 16-byte section trace mes-

sage (J0) from the receive data and optionally

stores it in, or compares it to, an internal register

bank. Unstable or mismatched messages are

detected, and path alarm indication signal (AIS)

may be optionally inserted in the drop data.

Optionally inserts a 64-byte or 16-byte section trace

message or a fixed pattern in the J0 byte of the

transmit data.

* Refer to LVDS Receiver Buffer Capabilities section on page 169 for additional details.

TSOT0410G4 SONET/SDH

STS-192 Overhead and Path Processor

Data Sheet

May 2003

Table of Contents

Contents

Page

Features ................................................................................................................................................................... 1

General .................................................................................................................................................................. 1

STS-192/STM-64 (Line Interface).......................................................................................................................... 1

Add/Drop (Equipment Interface) .......................................................................................................................... 12

Applications ............................................................................................................................................................ 12

Description.............................................................................................................................................................. 13

Block Diagrams.................................................................................................................................................... 13

Glossary............................................................................................................................................................... 14

Receive Direction Overview................................................................................................................................. 15

Transmit Direction Overview................................................................................................................................ 15

STS-192 Mode Options ....................................................................................................................................... 16

TOH Transparency............................................................................................................................................ 16

Regenerator Loopback...................................................................................................................................... 16

Device Mode Setup.............................................................................................................................................. 16

Pin Information ....................................................................................................................................................... 17

Functional Description ............................................................................................................................................ 47

Receive STS-192 Line Interface .......................................................................................................................... 47

Loss-of-Signal (LOS) Detector .......................................................................................................................... 47

Framer (A1 and A2)........................................................................................................................................... 48

Descrambler ...................................................................................................................................................... 50

Time-Slot Interchanger (TSI)............................................................................................................................. 50

Receive Transport Overhead (TOH) Processor................................................................................................... 52

Receive Overhead Serial Links ......................................................................................................................... 52

Section Trace (J0) ............................................................................................................................................. 53

Section Growth (Z0) .......................................................................................................................................... 54

Section BIP-8 (B1)............................................................................................................................................. 54

Section BIP-8 (B1) Errors Serial Access ........................................................................................................... 54

Local Orderwire (E1) ......................................................................................................................................... 55

Section User Channel (F1)................................................................................................................................ 55

Section Data Communications Channel (D1, D2, and D3) ............................................................................... 55

Line BIP-8 (B2).................................................................................................................................................. 56

Line BIP-8 (B2) Errors Serial Access ................................................................................................................ 58

APS Channel (K1 and K2)................................................................................................................................. 58

Line Data Communication Channel (D4—D12) ................................................................................................ 60

Synchronization Status (S1).............................................................................................................................. 60

STS-192 Line Remote Error Indication (M1) ..................................................................................................... 61

Express Orderwire (E2)..................................................................................................................................... 61

Receive STS Path Processor .............................................................................................................................. 61

1:4 Demultiplex TSI ........................................................................................................................................... 62

Receive Pointer Processor................................................................................................................................ 62

Receive Path Overhead (POH) Processor........................................................................................................ 69

Receive Payload Drop Interface .......................................................................................................................... 76

STS-12 Overhead Insertion and Scrambling..................................................................................................... 77

Drop Interface Output Format ........................................................................................................................... 78

Data Path Parity ................................................................................................................................................ 79

Regenerator Loopback (STS-192 Mode Only) .................................................................................................... 80

Transmit Payload Add Interface........................................................................................................................... 80

STS-12 Framing, Descrambling, and TOH Processing..................................................................................... 81

Transmit Synchronization Buffer ....................................................................................................................... 82

Add Interface Framing (A1 and A2)................................................................................................................... 82

4:1 Time-Slot Multiplex (TSM)........................................................................................................................... 84

Agere Systems Inc.

Data Sheet

May 2003

TSOT0410G4 SONET/SDH

STS-192 Overhead and Path Processor

Table of Contents

(continued)

Contents

Page

Transmit Transport Overhead (TOH) Processor.................................................................................................. 84

TOH Transparency............................................................................................................................................ 85

Transmit Overhead Serial Links ........................................................................................................................ 86

Section Trace/Section Growth (J0/Z0) .............................................................................................................. 86

Section BIP-8 (B1)............................................................................................................................................. 87

Local Orderwire (E1) ......................................................................................................................................... 87

Section User Channel (F1)................................................................................................................................ 87

Section Data Communications Channel (D1, D2, and D3) ............................................................................... 88

STS Payload Pointer (H1 and H2) .................................................................................................................... 88

Line BIP-8 (B2).................................................................................................................................................. 89

APS Channel (K1 and K2)................................................................................................................................. 90

Line Data Communication Channel (D4—D12) ................................................................................................ 90

Synchronization Status (S1).............................................................................................................................. 91

STS-192 Line Remote Error Indication (M1) ..................................................................................................... 91

Express Orderwire (E2)..................................................................................................................................... 92

Transmit STS-192 Line Interface ......................................................................................................................... 92

Time-Slot Multiplexer (TSM).............................................................................................................................. 92

Scrambler .......................................................................................................................................................... 92

Data Path Parity ................................................................................................................................................ 92

Microprocessor Interface ........................................................................................................................................ 93

Architecture.......................................................................................................................................................... 93

Transfer Error Acknowledge (TEA_N)............................................................................................................... 93

Interrupt Structure ............................................................................................................................................. 93

Parity Bits .......................................................................................................................................................... 94

Clock Domains .................................................................................................................................................. 94

Persistency Registers .......................................................................................................................................... 96

Register Description............................................................................................................................................. 96

Software Reset .................................................................................................................................................... 96

Device-Level Registers ...................................................................................................................................... 110

Line Terminating Equipment (LTE) Registers.................................................................................................... 115

LTE Common Registers .................................................................................................................................. 115

LTE J0 Access Registers ................................................................................................................................ 117

Signal Degrade/Signal Fail Registers.............................................................................................................. 119

LTE Receive Channel 1, 2, 3, and 4 Registers ............................................................................................... 122

LTE Transmit Common Registers...................................................................................................................... 128

LTE Transmit Channel Registers .................................................................................................................... 130

Equipment (EQPT) Registers ............................................................................................................................ 134

EQPT Common Registers............................................................................................................................... 134

EQPT Receive Drop STS-48 Channel Registers 1—4 ................................................................................... 137

EQPT Transmit Add STS-48 Channel Registers 1—4.................................................................................... 139

Path Overhead (POH) Registers ....................................................................................................................... 144

STS-12, STS-1 Level POH Registers ............................................................................................................. 145

STS-192 Level POH Registers........................................................................................................................ 149

STS-192 Level Path Trace Registers.............................................................................................................. 154

STS-48 Level POH Registers.......................................................................................................................... 155

Absolute Maximum Ratings.................................................................................................................................. 166

Handling Precautions ........................................................................................................................................... 166

Recommended Operating Conditions .................................................................................................................. 166

Electrical Characteristics ...................................................................................................................................... 167

Power Sequencing............................................................................................................................................. 167

Low-Voltage Differential Signal (LVDS) Buffers................................................................................................. 167

Agere Systems Inc.

TSOT0410G4 SONET/SDH

STS-192 Overhead and Path Processor

Data Sheet

May 2003

Table of Contents

(continued)

Contents

Page

LVDS Receiver Buffer Capabilities.................................................................................................................. 169

Timing Characteristics .......................................................................................................................................... 172

Receive Data Interface ...................................................................................................................................... 172

Receive STS-48/STS-192 Data ...................................................................................................................... 172

Receive Transport Overhead Interface.............................................................................................................. 173

Receive Local Orderwire ................................................................................................................................. 173

Receive Section User...................................................................................................................................... 173

Receive Express Orderwire............................................................................................................................. 174

Receive Section Data Com ............................................................................................................................. 174

Receive Line Data Com .................................................................................................................................. 174

Receive Overhead Serial Link......................................................................................................................... 175

Transmit Data Interface ..................................................................................................................................... 176

Transmit STS-48/STS-192 Data ..................................................................................................................... 176

Transmit Frame ............................................................................................................................................... 177

Transmit Transport Overhead Interface............................................................................................................. 178

Transmit Local Orderwire ................................................................................................................................ 178

Transmit Section User..................................................................................................................................... 178

Transmit Express Orderwire............................................................................................................................ 178

Transmit Section Data Com ............................................................................................................................ 179

Transmit Line Data Com ................................................................................................................................. 179

Transmit Overhead Serial Link........................................................................................................................ 180

Receive Drop Interface ...................................................................................................................................... 181

Drop Clock, Drop Frame, and Drop Data ........................................................................................................ 181

Receive Drop Section Data Com .................................................................................................................... 182

Transmit Add Interface....................................................................................................................................... 183

Transmit Add Data .......................................................................................................................................... 183

Transmit Add Section Data Com..................................................................................................................... 183

Microprocessor Interface Timing........................................................................................................................ 183

Synchronous Mode ......................................................................................................................................... 183

Asynchronous Mode........................................................................................................................................ 186

Use of a Synchronous Microprocessor with the TSOT0410G4 in Asynchronous Mode ................................. 188

Outline Diagram.................................................................................................................................................... 189

600-Pin LBGA .................................................................................................................................................... 189

Ordering Information............................................................................................................................................. 190

Agere Systems Inc.

Data Sheet

May 2003

TSOT0410G4 SONET/SDH

STS-192 Overhead and Path Processor

List of Figures

Contents

Page

Figure 1. TSOT0410G4 Block Diagram, STS-192 Mode ...................................................................................... 13

Figure 2. TSOT0410G4 Block Diagram, STS-48 Mode ........................................................................................ 14

Figure 3. Suggested Schematic for 1.0 V and 1.4 V Reference Voltages ............................................................. 35

Figure 4. Framer FSM ........................................................................................................................................... 49

Figure 5. Example of STS-192 SD Detection (10

–5

BER) and Clearing (10

–6

BER) ............................................. 57

Figure 6. Timing Diagram for RFRM ..................................................................................................................... 60

Figure 7. Pointer Interpreter State Machine .......................................................................................................... 63

Figure 8. STS-12 Data Outputs and Timing .......................................................................................................... 79

Figure 9. TSOT0410G4 Timing Domains .............................................................................................................. 95

Figure 10. Persistency Register Operation ............................................................................................................ 96

Figure 11. Path Register Structure ...................................................................................................................... 144

Figure 12. LVDS Driver and Receiver and Associated Internal Components ..................................................... 168

Figure 13. LVDS Driver and Receiver ................................................................................................................. 168

Figure 14. LVDS Driver ....................................................................................................................................... 168

Figure 15. Receive Data Timing .......................................................................................................................... 172

Figure 16. Receive Data Communication Channels Timing ................................................................................ 173

Figure 17. Receive Overhead Serial Timing ........................................................................................................ 175

Figure 18. Transmit Data Timing ......................................................................................................................... 176

Figure 19. Transmit Frame Timing ...................................................................................................................... 177

Figure 20. Transmit Data Communication Channels Timing ............................................................................... 178

Figure 21. Transmit Overhead Serial Timing ....................................................................................................... 180

Figure 22. Receive Frame Timing (Pointer Processor Bypassed) ...................................................................... 181

Figure 23. Receive Frame Timing (Pointer Processor Active) ............................................................................ 182

Figure 24. Microprocessor Interface Synchronous Write Cycle (MPMODE = 1) ................................................. 184

Figure 25. Microprocessor Interface Synchronous Read Cycle (MPMODE = 1) ................................................. 185

Figure 26. Microprocessor Interface Asynchronous Write Cycle (MPMODE = 0) ............................................... 186

Figure 27. Microprocessor Interface Asynchronous Read Cycle (MPMODE = 0) ............................................... 187

Agere Systems Inc.

推荐资源

刚刚学汇编语言，第一次使用RadASM2.2.1.8，为什么编译不成功？？: 我刚刚学汇编语言，下面的代码是书上的一个例子，我用RadASM2.2.1.8来编译它。一、源代码 DSEG SEGMENT MESS DB "MY NAME IS JACK",02H,0DH,0AH,"$" DSEG ENDS CSEG SEGMENT ASSUME ......; 651061924 嵌入式系统

光耦A316J报故障是怎样报法: 我想问一下A316J光耦的VCE饱和压降保护和电流保护，它故障引脚输出的电平一样吗？501028 ...; sunboy25 模拟电子

ESP32学习笔记2---WS2812 16*16 点阵: 距离上一次发帖也有好长时间了，因为工作比较忙所以就把学习进度缓了缓。之后呢我会努力的更细自己的学习状况和经验分享。之前买过一条WS2812的灯带，觉得很好玩，就想自己焊一个点阵来玩 ......; 是最帅的啊 MicroPython开源版块

【一起玩ESP8266】修改网络参数解决reconnect问题: 貌似有多位坛友出现类似问题：ESP8266通过mini USB线连接PC机后，打开串口工具，总会莫名弹出一句话，而且是不停弹，压根没法用命令行，重刷各种版本固件也不能解决。如下图 261988 261989 ......; mikeliujia MicroPython开源版块

ANC主动降噪耳机解决方案: 最近中奖一个ANC主动降噪耳机，很想了解原理。落伍了跟不上时代，谁有资料方案或者原理图分享下。十年前玩过音频电路：立体声、3D环绕声、2.1声道(超重低音）、立体声解码、杜比解码、电子EQ ......; yedaochang 模拟电子

关于STM汽车级的问题: STM8有汽车级的芯片，我想知道汽车级和标准级的有什么优势，知道的请明示，另外STM32有没有可能出汽车级的片子？...; 天凉好个秋 stm32/stm8

CATV的智能校园广播/考试系统的设计

传统的广播系统，一般需要由人工定时操作，且只能实现一路广播，功能少，传统的打铃设备，音源单一，声音刺耳，随着学校教学改革的不断深入，这些电教设备已不能满足学校的要求和发展，根据学校的需求，笔者利用电脑多媒体技术和单片机技术，结合CATV系统设计出了智能校园广播/考试系统，该系统不仅可以实现多路调频广播，而且可以寻址广播，控制校园任一广播终端的功能操作，如广播开关、声音调节和频道切换等，同时广播终...[详细]
自制健康节能的饮水机

一、电路的组成整个电路包括两部分： 1．节电控制电路如下图所示。包括延时电路、驱动电路。 (1)延时电路。包括集成电路U1(CD4541)。电阻R2、R3、R4，电容C4，按钮S0、S1。 (2)驱动电路：由R1、晶体管Q1、继电器J1、二极管D1组成。 2．凉、热水分开及水位指示电路如下图所示。包括基准电压电路、水位比较电路、驱动电路。 (1)基准电压电路。由电阻R6、R8、R11...[详细]
智能化是未来汽车市场发展的方向

随着汽车产业发展以及人们对驾驶体验要求的提高？熏越来越多的车企开始涉足汽车智能化领域，将尖端的IT技术运用到汽车上，使汽车的操作性更简单，行驶安全性更好。近5年来，汽车产业领域超过90%的创新都与汽车智能化系统相关，智能化是未来汽车发展的趋势。汽车智能化被认为是汽车技术发展进程中的一次革命，是夺取未来汽车市场重要而有效的手段。 “两化”融合离不开政策支持近日，国家工业和信息化部产业政策...[详细]
基于超声探测的停车场车位引导系统的研究

1、引言随着停车需求的增长，停车场的规模也越来越趋于大型化。国内对智能停车场也进行了大量的研究，但目前我国的停车场管理系统大多还存在智能化、集成度低的缺点，忽视了停车过程的自动化，特别是车位的引导。如何检测车位和引导司机方便的泊车也是停车管理的重要组成部分，该方案通过对最短路径有效算法和场内车位引导。及现场总线通讯等方面进行阐述，对特大型智能自动化停车场的设计具有一定的参考价值。 2、...[详细]
如何让模拟工程师实现数字电源转换

模拟工程师以前在设计需要具有多路输出、动态负载共享、热插拔或广泛故障处理能力的电源时，往往需要与复杂性抗争。利用模拟电路来实现系统控制功能并非总是经济有效或灵活的。采用模拟技术设计电源需要使用“过大的”元件来解决元件变化和元件漂移的问题。即使是在克服了这些设计难点之后，这些电源在生产线末端还需要进行人工调整。　　那么，模拟工程师应该选择什么来设计电源呢？工程学对这个问题的回...[详细]
Blackfin汇聚式处理器如何以可扩展性取胜

汇聚式处理器满足扩展性需求当前嵌入式系统设计中，基于MCU、DSP、FPGA及ASIC的解决方案占据了超过90%的市场份额，这些方案各自在成本、功耗、集成度以及开发环境支持上具有不同的特点，而单就设计的可扩展性而言，DSP通常能提供比竞争性解决方案更强大的处理能力，为功能扩展提供了足够的性能裕量，而且基于软件的实现方式具有无可比拟的灵活性和扩展性优势。近年来，随着主流的DSP提供商在...[详细]
基于FPGA的汽车视频和图形控制系统设计

LCD显示器真是无处不在，在家庭、超市、体育馆以及汽车内你都可以见到它们的身影。无疑车载LCD显示系统是增长最快的市场。增长的动力包括：不断下降的显示器价格、不断提升的用户体验、更多的产品性能以及车内消费类产品的集结。典型的图形显示系统一般都是利用标准的特殊应用标准处理器(ASSP)或者定制的特殊应用集成电路(ASIC)作为控制器来构建的。但汽车图形设计师在利用这些器件构建系统时遭...[详细]
《中国企业家》：雷军小米加步枪

雷军小米加步枪　　“左派”雷军要全面介入从手机设计、零部件采购、供应链管理、销售、电子商务乃至售后服务的各个环节　　文 | 本刊记者冀勇庆(微博) 　　对于身处亏损边缘的手机厂商来说，360等互联网厂商即使短期内无法给他们带来预期的收益，至少也是无害的。而让他们异常忌惮的，正是采用了全套互联网打法的小米公司。　　去年8月16日，在一场类似苹果的盛大发布会上，身穿黑色T恤，被人称为...[详细]
穿越?去年7月已经有人知道Google要推出Nexus 7？

广受欢迎的“Ninja Unboxing” 节目放出了Nexus 7的相关视频，并由著名解说人George St-Pierre来扮演“Dr Paul”来开箱Nexus 7，以一种幽默方式来讲述忍者和平板之间发生的有趣故事。不过最有趣的是这段视频竟然是去年7月份时候放到Youtube上，是微软在去年就已经有这个念头了还是他们未卜先知不不得而知了。 ...[详细]
摩托罗拉遭谷歌“雪藏”：命运待解

摩托罗拉移动遭谷歌“雪藏” 　　上个月月底，谷歌在美国旧金山举行开发者大会，会上谷歌新一代Andriod操作系统，Nexus 7平板电脑、Nexus Q播放器及谷歌眼镜等3款硬件产品大放异彩。而当谷歌宣布Nexus 7平板电脑由谷歌与华硕合作研发而成的时候，估计有人会有疑问：为什么不是摩托罗拉移动？　　虽然摩托罗拉移动的主要业务是手机，但该公司在平板电脑领域也并非没有经验。2011年年初...[详细]
白光LED光衰原因之荧光粉性能的衰退

白光LED光衰原因之荧光粉性能的衰退到目前，白光 LED、尤其是小功率白光 LED 的发光性能快速衰退已越来越为人们所认识。其实，盲目地夸大宣传，只能将 LED 行业引向歧途，不正视白光 LED 存在的问题，只能延缓白光 LED 应用的发展。只有正视问题、研究问题、尽早解决问题，白光 LED 才能健康、快速发展。白光 LED 当前面临的一个主要问题就寿命问题。由于白光 LED 的价格尚很...[详细]
基于Linux的动态电源管理:使嵌入式设备更节能

　　为了在产品众多、竞争激烈的市场上使产品与众不同，手持设备的制造商们往往把电池寿命和电源管理作为手机、PDA、多媒体播放器、游戏机、其它便携式消费类设备等产品的关键卖点来考虑。用户是从电池寿命这方面来看待电源管理的成效，其实它是多种因素共同作用的结果，这些因素包括 CPU 功能、系统软件、中间件，以及使用户可以在更长的充电或更换电池的间隔时间内享用各自设备的策略。　　电源管理范围　　任...[详细]
优化针对高端应用处理器的电源管理

　　针对当今便携式应用处理器的电源管理解决方案的集成度越来越高了。总功耗、待机和休眠电流消耗会影响电池的大小、原材料成本与产品验收。设计智能手机或PDA之类的便携式器件时，系统设计师必须考虑电源的多种变量。智能手机越来越耗电，需要高度集成的电源管理解决方案，以便在尽可能最小的PCB面积中满足整体设计对最长电池寿命的要求。当今的应用处理器要求内核、I/O、存储器和外设具有独立的电源域。LP3971...[详细]
中兴通讯Uni-RAN助力越南Viettel拓展南美3G市场

近日，中兴通讯宣布独家中标越南第一大移动运营商Viettel在秘鲁的无线网络项目，一期规模超过2000个基站。该项目是Viettel首次进入南美通讯市场，项目建成后Viettel的2G/3G网络将覆盖秘鲁全国，该合同的签订也标志着中兴通讯与Viettel的合作进一步深化。 Viettel总部位于越南河内，是越南最大的移动运营商，在越南市场占有率达50.7%，是世界上增长最快的电信运营商之一。目...[详细]
泛华恒兴参加华南自动化展货架、系统产品齐亮相

作为致力于为各行业用户提供专业测试测量解决方案和成套检测设备的高新技术企业，北京泛华恒兴科技有限公司（简称：泛华恒兴）参加了2012年深圳华南自动化展，并参加了中国电源学会电源技术分会活动，这也是泛华首次有规模地参加华南市场的大型展会。泛华恒兴展台会上，由泛华恒兴推出的全新的系统级产品——电源自动化测试台高调亮相。电源自动化测试台倡导可靠、精准、自动、高效的电源测试，已...[详细]

器件捷径: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

热门器件

开源项目推荐更多

热门活动更多

热门文章更多

技术资料推荐更多