Data Sheet
February 2004
Ambassador
®
T8110L H.100/H.110 Switch
1 Introduction
The T8110L is the newest addition to the
Ambassa-
dor
series of TDM switching and backlane intercon-
nect standard products. The T8110L can switch 4096
simultaneous time slots with 32 bidirectional local
streams and 32 bidirectional H.100/H.110 streams.
The T8110L has all the features of the T810X
devices. Additionally, the T8110L has more robust
clocking fallback abilities and is pin compatible with
the T8110. (The full version of the T8110 has a PCI
and minbridge interface.)
!
!
!
!
!
!
Eight independently programmed framing signals
Four local clocks
T1/E1 rate adaptation
Two clock-fallback modes
Stratum 4/4E and
AT&T
®
62411 MTIE compliant
Incorporates 38 H.100 and 34 H.110 termination
resistors
Subrate switching of 4 bits, 2 bits, or 1 bit
Backward compatible to all T810x devices
Pin compatible with T8110
JTAG/boundary-scan testing support
BSDL files available
Assists H.110 hot swap
Single 3.3 V supply with 5 V tolerant inputs and
TTL compatible outputs
272 PBGA package
Evaluation boards available
!
!
!
1.1 Features
!
!
!
!
!
!
4,096-connection unified switch
Full H.100/H.110 support (32 data lines, all clock
modes)
32 local I/O lines (2, 4, 8, or 16 Mbits/s)
Microprocessor interface:
Motorola
®
/Intel
®
modes
Interrupt controller with external inputs
Eight independent general-purpose I/O lines
!
!
!
!
!
!
Ambassador
T8110L H.100/H.110 Switch
Data Sheet
February 2004
Table of Contents
Contents
1
2
Page
3
4
5
6
Introduction ......................................................................................................................................................... 1
1.1
Features....................................................................................................................................................1
Pin Description ..................................................................................................................................................10
2.1
Interface Signals .....................................................................................................................................10
2.2
T8110L Pinout Information .....................................................................................................................12
2.3
Special Buffer Requirements ..................................................................................................................20
2.3.1 H1x0 Bus Signal Internal Pull-Up/Pull-Down ..............................................................................20
2.3.2 Local Bus Signal Internal Pull-Up ...............................................................................................20
Main Architectural Features ..............................................................................................................................21
3.1
T8110L Architecture ...............................................................................................................................21
Microprocessor Interface ..................................................................................................................................22
4.1
Intel/Motorola
Protocol Selector..............................................................................................................22
4.2
Word/Byte Addressing Selector..............................................................................................................22
4.3
Access Via the Microprocessor Bus .......................................................................................................23
4.3.1 Microprocessor Interface Register Map ......................................................................................24
4.3.2 Register Space Access ...............................................................................................................28
4.3.3 Connection Memory Space Access ............................................................................................28
4.3.4 Data Memory Space Access.......................................................................................................29
Operating Control and Status ...........................................................................................................................30
5.1
Control Registers ....................................................................................................................................30
5.1.1 Reset Registers ..........................................................................................................................30
5.1.2 Master Output Enable Register...................................................................................................31
5.1.3 Connection Control—Data Memory Selector Register ...............................................................32
5.1.4 General Clock Control (Phase Alignment, Fallback, Watchdogs) Register ................................33
5.1.5 Phase Alignment Select Register ...............................................................................................33
5.1.6 Fallback Control Register............................................................................................................33
5.1.7 Fallback Type Select Register ....................................................................................................34
5.1.8 Fallback Trigger Registers ..........................................................................................................35
5.1.9 Watchdog Select, C8, and NETREF Registers...........................................................................36
5.1.10 Watchdog EN Register ...............................................................................................................37
5.1.11 Failsafe Control Registers...........................................................................................................38
5.2
Error and Status Registers .....................................................................................................................39
5.2.1 Clock Errors ................................................................................................................................40
5.2.1.1 Transient Clock Errors Registers.................................................................................40
5.2.1.2 Latched Clock Error Register ......................................................................................41
5.2.2 System Status .............................................................................................................................42
5.2.2.1 Clock Fallback Status Register....................................................................................42
5.2.2.2 Device Identification Registers ....................................................................................43
5.2.2.3 System Device Errors..................................................................................................43
Clock Architecture .............................................................................................................................................44
6.1
Clock Input Control Registers .................................................................................................................45
6.1.1 Main Input Selector Register.......................................................................................................45
6.1.2 Main Divider Register..................................................................................................................46
6.1.3 Analog PLL1 (APLL1) Input Selector Register............................................................................46
6.1.4 APLL1 Rate Register ..................................................................................................................47
6.1.5 Main Inversion Select Register ...................................................................................................47
6.1.6 Resource Divider Register ..........................................................................................................48
6.1.7 Analog PLL2 (APLL2) Rate Register ..........................................................................................48
6.1.8 LREF Input Select Registers.......................................................................................................49
6.1.9 DPLL1 Input Selector ..................................................................................................................50
Agere Systems Inc.
2
Data Sheet
February 2004
Ambassador
T8110L H.100/H.110 Switch
Table of Contents
(continued)
Contents
Page
7
8
6.1.9.1 DPLL1 Rate Register...................................................................................................50
6.1.10 DPLL2 Input Selector ..................................................................................................................50
6.1.10.1 DPLL2 Rate Register...................................................................................................51
6.1.11 NETREF1 Registers....................................................................................................................51
6.1.12 NETREF2 Registers....................................................................................................................52
6.2
Clock Output Control Registers ..............................................................................................................53
6.2.1 Master Output Enables Register .................................................................................................53
6.2.2 Clock Output Format Registers...................................................................................................54
6.2.3 TCLK and L_SCx Select Registers .............................................................................................55
6.3
Clock Register Access............................................................................................................................57
6.4
Clock Circuit Operation—APLL1 ............................................................................................................57
6.4.1 Main Clock Selection, Bit Clock, and Frame ...............................................................................57
6.4.1.1 Watchdog Timers ........................................................................................................58
6.4.1.2 Frame Center Sampling ..............................................................................................59
6.4.1.3 LREF Pair Polarity Configuration.................................................................................60
6.4.2 Main and Resource Dividers .......................................................................................................61
6.4.3 DPLL1 .........................................................................................................................................61
6.4.4 Reference Selector .....................................................................................................................61
6.4.5 Internal Clock Generation ...........................................................................................................61
6.4.5.1 Phase Alignment .........................................................................................................62
6.5
Clock Circuit Operation, APLL2 ..............................................................................................................63
6.5.1 DPLL2 .........................................................................................................................................63
6.6
Clock Circuit Operation, CT_NETREF Generation.................................................................................63
6.6.1 NETREF Source Select ..............................................................................................................63
6.6.2 NETREF Divider..........................................................................................................................63
6.7
Clock Circuit Operation—Fallback and Failsafe .....................................................................................64
6.7.1 Clock Fallback.............................................................................................................................64
6.7.1.1 Fallback Events ...........................................................................................................64
6.7.1.2 Fallback Scenarios—Fixed vs. Rotating Secondary....................................................65
6.7.1.3 H-Bus Clock Enable/Disable on Fallback ....................................................................68
6.7.2 Clock Failsafe .............................................................................................................................70
6.7.2.1 Failsafe Events ............................................................................................................70
Frame Group and FG I/O ..................................................................................................................................72
7.1
Frame Group Control Registers..............................................................................................................72
7.1.1 FGx Lower and Upper Start Registers ........................................................................................72
7.1.2 FGx Width Registers ...................................................................................................................73
7.1.3 FGx Rate Registers ....................................................................................................................73
7.2
FG7 Timer Option ...................................................................................................................................74
7.2.1 FG7 Counter (Low and High Byte) Registers..............................................................................74
7.3
FGIO Control Registers ..........................................................................................................................75
7.3.1 FGIO Data Register ....................................................................................................................75
7.3.2 FGIO Read Mask Register..........................................................................................................75
7.3.3 FGIO R/W Register .....................................................................................................................76
7.4
FG Circuit Operation...............................................................................................................................77
7.4.1 Frame Group 8 kHz Reference Generation ................................................................................78
7.4.2 FGIO General-Purpose Bits ........................................................................................................79
7.4.3 Programmable Timer (FG7 Only)................................................................................................79
7.4.4 FG External Interrupts.................................................................................................................79
7.4.5 FG Diagnostic Test Point Observation........................................................................................79
General-Purpose I/O .........................................................................................................................................80
8.1
GPIO Control Registers ..........................................................................................................................80
3
Agere Systems Inc.
Ambassador
T8110L H.100/H.110 Switch
Data Sheet
February 2004
Table of Contents
(continued)
Contents
Page
8.1.1 GPIO Data Register ....................................................................................................................80
8.1.2 GPIO Read Mask Register .........................................................................................................81
8.1.3 GPIO R/W Register.....................................................................................................................81
8.1.4 GPIO Override Register ..............................................................................................................82
8.2
GP Circuit Operation...............................................................................................................................82
8.2.1 GPIO General-Purpose Bits........................................................................................................83
8.2.2 GP Dual-Purpose Bits GPIO (Override)...................................................................................... 83
8.2.2.1 GP H.110 Clock Master Indicators (GP0, GP1 Only) ..................................................83
8.2.3 GP External Interrupts ................................................................................................................83
8.2.4 GP Diagnostic Test Point Observation .......................................................................................83
9 Stream Rate Control .........................................................................................................................................84
9.1
H-Bus Stream Rate Control Registers....................................................................................................85
9.1.1 H-Bus Rate Registers .................................................................................................................85
9.2
L-Bus Stream Rate Control Registers ....................................................................................................85
9.2.1 L-Bus Rate Registers ..................................................................................................................85
9.2.2 L-Bus 16.384 Mbits/s Operation .................................................................................................86
9.2.3 16.384 Mbits/s Local I/O Superrate ............................................................................................88
9.2.4 16.384 Mbits/s Local I/O Superrate ............................................................................................89
10 Error Reporting and Interrupt Control ...............................................................................................................90
10.1 Interrupt Control Registers......................................................................................................................90
10.1.1 Interrupts Via External FG[7:0] Registers ...................................................................................90
10.1.1.1 FGIO Interrupt Pending Register.................................................................................90
10.1.2 Interrupts Via External GP[7:0] ...................................................................................................92
10.1.2.1 GPIO Interrupt Pending Register.................................................................................92
10.1.2.2 GPIO Edge/Level and GPIO Polarity Registers ..........................................................93
10.1.3 Interrupts Via Internal System Errors ..........................................................................................93
10.1.4 System Interrupt Pending High/Low Registers ...........................................................................94
10.1.5 System Interrupt Enable High/Low Registers .............................................................................95
10.1.6 Interrupts Via Internal Clock Errors .............................................................................................96
10.1.7 Clock Interrupt Pending High/Low Registers ..............................................................................97
10.1.8 Clock Interrupt Enable High/Low Registers ................................................................................98
10.1.9 Interrupt Servicing Registers.......................................................................................................99
10.1.9.1 Arbitration Control Register .........................................................................................99
10.1.9.2 SYSERR and CLKERR Output Select Register ..........................................................99
10.1.9.3 Interrupt In-Service Registers....................................................................................101
10.2 Error Reporting and Interrupt Controller Circuit Operation ...................................................................103
10.2.1 Externally Sourced Interrupts Via FG[7:0], GP[7:0] ..................................................................104
10.2.2 Internally Sourced System Error Interrupts ...............................................................................104
10.2.3 Internally Sourced Clock Error Interrupts ..................................................................................104
10.2.4 Arbitration of Pending Interrupts ...............................................................................................104
10.2.4.1 Arbitration Off ............................................................................................................104
10.2.4.2 Flat Arbitration ...........................................................................................................104
10.2.4.3 Tier Arbitration ...........................................................................................................104
10.2.4.4 Pre-Empting Disabled................................................................................................105
10.2.4.5 Pre-Empting Enabled ................................................................................................105
10.2.5 CLKERR Output........................................................................................................................105
10.2.6 SYSERR Output .......................................................................................................................105
10.2.7 System Handling of Interrupts...................................................................................................105
11 Test and Diagnostics ......................................................................................................................................106
11.1 Diagnostics Control Registers ..............................................................................................................106
11.1.1 FG Testpoint Enable Register...................................................................................................106
4
Agere Systems Inc.
Data Sheet
February 2004
Ambassador
T8110L H.100/H.110 Switch
Table of Contents
(continued)
Contents
Page
11.1.2 GP Testpoint Enable Register ..................................................................................................108
11.1.3 State Counter Modes Registers ................................................................................................110
11.1.4 Miscellaneous Diagnostics Low Register..................................................................................110
11.1.5 Miscellaneous Diagnostic Registers .........................................................................................111
11.2 Diagnostic Circuit Operation .................................................................................................................112
12 Connection Control .........................................................................................................................................113
12.1 Programming Interface .........................................................................................................................113
12.1.1 Connection Memory Programming ...........................................................................................113
12.2 Switching Operation..............................................................................................................................115
12.2.1 Memory Architecture and Configuration....................................................................................115
12.2.1.1 Connection Memory ..................................................................................................115
12.2.1.2 Data Memory .............................................................................................................116
12.2.2 Standard Switching ...................................................................................................................117
12.2.2.1 Constant Delay and Minimum Delay Connections ....................................................117
12.2.2.2 Pattern Mode .............................................................................................................117
12.2.2.3 Subrate ......................................................................................................................117
13 Electrical Characteristics.................................................................................................................................124
13.1 Absolute Maximum Ratings ..................................................................................................................124
13.1.1 Handling Precautions ................................................................................................................124
13.2 Crystal Specifications ...........................................................................................................................124
13.2.1 XTAL1 Crystal ...........................................................................................................................124
13.2.2 XTAL2 Crystal ...........................................................................................................................125
13.2.3 Reset Pulse...............................................................................................................................126
13.3 Thermal Parameters (Definitions and Values)......................................................................................126
13.4 Reliability ..............................................................................................................................................127
13.5 dc Electrical Characteristics..................................................................................................................128
13.5.1 Electrical Drive Specifications, CT_C8 and /CT_FRAME .........................................................128
13.5.2 All Other Pins ............................................................................................................................129
13.6 H-Bus Timing ........................................................................................................................................129
13.6.1 Timing Diagrams .......................................................................................................................129
13.7 ac Electrical Characteristics..................................................................................................................130
13.7.1 Skew Timing, H-Bus..................................................................................................................130
13.8 Hot Swap ..............................................................................................................................................131
13.8.1 LPUE (Local Pull-Up Enable)....................................................................................................131
13.9 Decoupling............................................................................................................................................131
13.10 APLL V
DD
Filter ....................................................................................................................................132
13.11 PC Board PBGA Considerations ..........................................................................................................133
13.12 Unused Pins .........................................................................................................................................133
13.13 External Pull-Up Pins............................................................................................................................133
13.14 T8110L Evaluation Kits.........................................................................................................................133
13.15 T8110L Ordering Information................................................................................................................133
14 JTAG/Boundary Scan .....................................................................................................................................137
14.1 The Principle of Boundary-Scan Architecture.......................................................................................137
14.1.1 Instruction Register ...................................................................................................................138
14.2 Boundary-Scan Register.......................................................................................................................138
A Constant and Minimum Delay Connections ....................................................................................................139
A.1 Connection Definitions..........................................................................................................................139
A.2 Delay Type Definitions..........................................................................................................................139
B Register Bit Field Mnemonic Summary...........................................................................................................142
Significant Changes Between the June 2003 and November 2003 Release ........................................................163
Agere Systems Inc.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
