Low Voltage 2.5V/3.3V Differential
LVPECL/HSTL Fanout Buffer
8T33FS6111
DATA SHEET
General Description
The 8T33FS6111 is a bipolar monolithic differential clock fanout
buffer. Designed for most demanding clock distribution systems, the
8T33FS6111 supports various applications that require distribution
of precisely aligned differential clock signals. Using SiGe:C
technology and a fully differential architecture, the device offers very
low skew outputs and superior digital signal characteristics. Target
applications for this clock driver is high performance clock distribution
in computing, networking and telecommunication systems.
The 8T33FS6111 is designed for low skew clock distribution systems
and supports clock frequencies up to 2.7GHz. The device accepts
two clock sources. The CLKA input can be driven by LVPECL
compatible signals, the CLKB input accepts HSTL or LVPECL
compatible signals. The selected input signal is distributed to 10
identical, LVPECL outputs. If V
BB
is connected to the CLKA input and
bypassed to GND by a 10nF capacitor, the 8T33FS6111 can be
driven by single-ended LVPECL signals utilizing the V
BB
bias voltage
output.
In order to meet the tight skew specification of the device, both
outputs of a differential output pair should be terminated, even if only
one output is used. In the case where not all ten outputs are used,
the output pairs on the same package side as the parts being used
on that side should be terminated.
The 8T33FS6111 can be operated from a single 3.3V or 2.5V supply.
Features
• 1:10 differential clock distribution
• 28ps typical output skew
• Fully differential architecture from input to all outputs
• SiGe:C technology supports near-zero output skew
• Supports DC to 2.7GHz operation of clock or data signals
• LVPECL compatible differential clock outputs
• LVPECL/HSTL compatible differential clock inputs
• Single 3.3V or 2.5V supply
• Standard 32-Lead VFQFN package
• Standard 32-lead LQFP package
• Standard 32-lead TQFP package with EPAD
• -40°C to 85°C ambient operating temperature
Block Diagram
Q0
nQ0
Q1
nQ1
V
CC
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
CC
CLKB
nCLKB
Pin Assignment
nQ0
nQ1
nQ2
V
CC
31
30
29
32
28
27
26
25
24
23
22
V
CC
Q0
Q1
Q2
CLKA
nCLKA
0
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
CLK_SEL
V
CC
CLK_SEL
CLKA
nCLKA
V
BB
CLKB
nCLKB
V
EE
1
2
3
4
1
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
V
BB
8T33FS6111
5
6
7
8
9
10
11
12
13
14
15
16
21
20
19
18
17
V
CC
nQ9
nQ8
.
8T33FS6111 REVISION 1 12/02/14
nQ7
V
CC
Q9
Q8
Q7
1
©2014 Integrated Device Technology, Inc.
8T33FS6111 DATA SHEET
Pin Description and Characteristics
Table 1. Pin Description
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Name
V
CC
CLK_SEL
CLKA
nCLKA
V
BB
CLKB
nCLKB
V
EE
V
CC
nQ9
Q9
nQ8
Q8
nQ7
Q7
V
CC
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
V
CC
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
CC
Power
Input
Input
Input
Output
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Output
Output
Output
Output
Output
Output
Power
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
DC
Type
Description
Positive power supply. All V
CC
pins must be connected to the
positive power supply for correct DC and AC operation.
Active clock input select.
Differential reference clock signal input.
Differential reference clock signal input.
Reference voltage output for single ended LVPECL operation.
HSTL/LVPECL Alternative differential reference clock signal input.
HSTL/LVPECL Alternative differential reference clock signal input.
Negative power supply.
Positive power supply. All V
CC
pins must be connected to the
positive power supply for correct DC and AC operation.
Differential clock outputs.
Differential clock outputs.
Differential clock outputs.
Positive power supply. All V
CC
pins must be connected to the
positive power supply for correct DC and AC operation.
Differential clock outputs.
Differential clock outputs.
Differential clock outputs.
Differential clock outputs.
Positive power supply. All V
CC
pins must be connected to the
positive power supply for correct DC and AC operation.
Differential clock outputs.
Differential clock outputs.
Differential clock outputs.
Positive power supply. All V
CC
pins must be connected to the
positive power supply for correct DC and AC operation.
Table 2. Function Table
Control
CLK_SEL
Default
0
0
CLKA, nCLKA input pair is active. CLKA can
be driven by LVPECL compatible signals.
1
CLKB, nCLKB input pair is active.
CLKB can be driven by HSTL or LVPECL
compatible signals.
LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL
FANOUT BUFFER
2
REVISION 1 12/02/14
8T33FS6111 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Electrical
Characteristics
or
AC Electrical Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
T
J
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
Operating Junction Temperature
–65
Condition
Min
–0.3
–0.3
–0.3
Typical
Max
3.6
V
CC
+ 0.3
V
CC
+ 0.3
±20
±50
125
125
Unit
V
V
V
mA
mA
°C
°C
Table 3. General Specifications
Symbol
V
TT
HBM
CDM
LU
C
IN
Characteristics
Output Termination Voltage
1
ESD Protection
(Human Body Model)
ESD Protection
(Charged Device Model)
Latch-up Immunity
Input Capacitance
Inputs
4000
2000
200
2
Condition
Min
Typ
V
CC
– 2
Max
Unit
V
V
V
mA
pF
NOTE 1: Output termination voltage V
TT
= 0V for V
CC
= 2.5V operation is supported but the power consumption of the device will increase
REVISION 1 12/02/14
3
LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL
FANOUT BUFFER
8T33FS6111 DATA SHEET
DC Electrical Characteristics
Table 4. LVPECL/HSTL DC Characteristics,
V
CC
= 2.5V ± 5% or V
CC
= 3.3V ± 5%, V
EE
= GND, T
A
= -40°C to +85°C
Symbol
Characteristics
Condition
Min
Typ
Max
Unit
Control Input CLK_SEL
V
IL
V
IH
I
IN
V
PP
V
CMR
I
IN
V
DIF
V
X
I
IN
V
OH
V
OL
Input Voltage Low
Input Voltage High
Input Current
Differential Input Voltage
1
Differential Crosspoint Voltage
1,2
Input Current
Differential Input Voltage
3
Differential Crosspoint Voltage
3,4
Input Current
V
IN
= V
X
±0.2V
I
OH
= –30mA
5
I
OL
= –5mA
5
V
CC
– 1.3
V
CC
– 1.9
V
IN
= V
IL
or V
IN
= V
IH
Differential operation
Differential operation
V
IN
= V
IL
or V
IN
= V
IH
0.4
0.10
0.68 – 0.9
0.15
1.0
V
EE
V
CC
– 1.165
V
CC
– 1.475
V
CC
100
V
V
A
Clock Input Pair CLKA, nCLKA (LVPECL differential signals)
1.3
V
CC
– (V
PP
/2)
150
V
V
A
Clock Input Pair CLKB, nCLKB (HSTL/LVPECL differential signals)
1.0
V
CC
– 1.1
200
V
V
A
LVPECL Clock Outputs (Q[0:9], nQ[0:9])
Output High Voltage
Output Low Voltage
V
CC
– 0.7
V
CC
– 1.5
V
V
Supply Current and V
BB
I
EE
V
BB
Maximum Quiescent Supply
Current without Output
Termination Current
6
Output Reference Voltage
V
EE
pin
I
BB
= 200A
V
CC
– 1.4
100
V
CC
– 1.2
mA
V
NOTE 1: V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality. V
IL
should not be less than -0.3V.
V
IH
should not be greater than V
CC
.
NOTE 2: V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the
V
CMR
(DC) range and the input swing lies within the V
PP
(DC) specification.
NOTE 3: V
DIF
(DC) is the minimum differential HSTL input voltage swing required for device functionality. V
IL
should not be less than -0.3V.
V
IH
should not be greater than V
CC
.
NOTE 4: V
X
(DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the
V
X
(DC) range and the input swing lies within the V
DIF
(DC) specification.
NOTE 5: Equivalent to a termination of 50 to V
TT
.
NOTE 6: I
CC
calculation: I
CC
= (number of differential output pairs used) x (I
OH
+ I
OL
) + I
EE
I
CC
= (number of differential output pairs used) x (V
OH
– V
TT
)/R
load
+ (V
OL
– V
TT
)/R
load
+ I
EE
LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL
FANOUT BUFFER
4
REVISION 1 12/02/14
8T33FS6111 DATA SHEET
AC Electrical Characteristics
Table 5. AC Characteristics,
V
CC
= 3.3V ±5% or V
CC
= 2.5V ±5%, V
EE
= GND, T
A
= -40°C to +85°C
1
Symbol
Characteristics
Input Frequency
2
Propagation Delay CLKA or
CLKB to Q[0:9]
Condition
Min
Typ
Max
Unit
Clock Input Pair CLKA, nCLKA (LVPECL differential signals)
f
CLK
t
PD
Differential
Differential
200
345
2.7
530
GHz
ps
Clock Input Pair CLKB, nCLKB (HSTL/LVPECL differential signals)
f
CLK
t
PD
Input Frequency
Propagation Delay
CLKB to Q[0:9]
Differential
Differential
200
375
2.7
530
GHz
ps
LVPECL Clock Outputs (Q[0:9], nQ[0:9])
Output Voltage (peak-to-peak)
V
O(P-P)
f
O
< 300MHz
f
O
< 1.5GHz
f
O
< 2.7GHz
t
sk(O)
t
sk(PP)
t
JIT
t
sk(P)
t
r
, t
f
Output-to-Output Skew
Part-to-Part Skew
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Output Pulse Skew
3
Output Rise/Fall Time
20% to 80%
110
Differential
Differential
f
CLK
= 156.25MHz,
Integration Range:
(12KHz - 20MHz)
75
300
ps
ps
74
100
fs
0.45
0.30
0.18
28
0.95
0.95
0.95
50
250
V
V
V
ps
ps
NOTE 1: AC characteristics apply for parallel output termination of 50 to V
TT
.
NOTE 2: The 8T33FS6111I is fully operational up to 3.0GHz and is characterized up to 2.7GHz.
NOTE 3: Output pulse skew is the absolute difference of the propagation delay times: | t
PLH
– t
PHL
|.
REVISION 1 12/02/14
5
LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL
FANOUT BUFFER
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