NB3F8L3010C
3.3V / 2.5V / 1.8V / 1.5V
3:1:10 LVCMOS Fanout Buffer
Description
The NB3F8L3010C is a 3:1:10 Clock / Data fanout buffer operating
on a 3.3 V / 2.5 V Core V
DD
and two flexible 3.3 V / 2.5 V / 1.8 V /
1.5 V VDDO
n
supplies which must be equal or less than V
DD
.
A Mux selects between a Crystal input, or either of two
differential/SE Clock / Data inputs. Differential Inputs accept
LVPECL, LVDS, HCSL, or SSTL and Single−Ended levels. The
MUX control lines, SEL0 and SEL1, select CLK0/CLK0,
CLK1/CLK1, or Crystal input pins per Table 3. The Crystal input is
disabled when a Clock input is selected. Output enable pin, OE,
synchronously forces a High Impedance state (HZ) when Low per
Table 4.
Outputs consist of 10 single−ended LVCMOS outputs.
Features
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MARKING
DIAGRAM
1
1 32
QFN32
G SUFFIX
CASE 488AM
A
WL
YY
WW
G
NB3F8L
3010C
AWLYYWWG
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Ten CMOS / LVTTL Outputs up to 200 MHz
Differential Inputs Accept LVPECL, LVDS, HCSL, or SSTL
Crystal Oscillator Interface
Crystal Input Frequency Range: 10 MHz to 50 MHz
Output Skew: 10 ps Typical
Additive RMS Phase Jitter @ 125 MHz, (12 kHz – 20 MHz): 0.03 ps
(Typical)
Synchronous Output Enable
Output Defined Level When Input is Floating
Power Supply Modes:
♦
Single 3.3 V
♦
Single 2.5 V
♦
Mixed 3.3 V
±
5% Core/2.5 V
±
5% Output Operating Supply
♦
Mixed 3.3 V
±
5% Core/1.8 V
±
0.2 V Output Operating Supply
♦
Mixed 3.3 V
±
5% Core/1.5 V
±
0.15 V Output Operating Supply
♦
Mixed 2.5 V
±
5% Core/ 1.8 V
±
0.2 V Output Operating Supply
♦
Mixed 2.5 V
±
5% Core /1.5 V
±
0.15 V Output Operating Supply
Two Separate Output Bank Power Supplies
Industrial temp. range -40°C to 85°C
These are Pb−Free Devices
Clock Distribution
Networking and Communications
High End Computing
Wireless and Wired Infrastructure
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information page 12 of this
data sheet.
Applications
End Products
©
Semiconductor Components Industries, LLC, 2016
1
May, 2016 − Rev. 7
Publication Order Number:
NB3F8L3010C/D
NB3F8L3010C
BANK A
VDD
VDDOA
VDDOB
GND
SEL0
SEL1
Q0
Q1
Q2
CLK0
CLK0
CLK1
CLK1
XTAL_IN
XTAL_OUT
BANK B
OSC
Q3
Q4
Q5
Q6
Q7
Q8
Q9
OE
SYNC
Figure 1. Simplified Logic Diagram
CLK1
SEL0
SEL1
GND
GND
CLK1
GND
OE
Exposed Pad (EP)
32
31
30
29
28
27
26
Q0
VDDOA
Q1
GND
Q2
VDDOA
Q3
Q4
25
1
2
3
4
24
23
22
21
Q9
VDDOB
Q8
GND
Q7
VDDOB
Q6
Q5
NB3F8L3010C
5
6
7
8
20
19
18
17
VDD 10
XTAL_OUT 12
CLK0 13
14
GND 15
XTAL_IN
Figure 2. Pinout Configuration
(Top View)
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2
CLK0
GND 16
GND
11
9
NB3F8L3010C
Table 1. PIN DESCRIPTION
Number
1, 3, 5, 7,
8
17, 18,
20, 22, 24
2, 6
19, 23
4, 9, 15,
16, 21,
25, 26, 32
10
11
12
13
14
27
28
29
30
31
−
Name
Q0, Q1, Q2,
Q3, Q4
Q5, Q6, Q7,
Q8, Q9
VDDOA
VDDOB
GND
Type
LVCMOS
LVCMOS
Power
Power
GND
Input
Default
Outputs − Bank A
Outputs − Bank B
Positive Supply Pins for Bank A Outputs Q0 − Q4
Positive Supply Pins for Bank B Outputs Q5 − Q9
Ground Supply
Description
VDD
XTAL_IN
XTAL_OUT
CLK0
CLK0
CLK1
CLK1
SEL1
SEL0
OE
EP
Power
XTAL OSC / CLK Input
XTAL OSC Output
Diff / SE Input
Diff / SE Input
Diff / SE Input
Diff / SE Input
LVCMOS / LVTTL
Input
LVCMOS / LVTTL
Input
LVCMOS / LVTTL
Input
−
Pulldown
Pullup /
Pulldown
Pullup /
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
V
DD
Positive Supply pin for Core and Inputs.
Crystal Oscillator Interface or External Clock Source at
LVCMOS Levels
Crystal Oscillator Interface
Non-inverting clock/data input 0.
Inverting differential clock input 0.
Inverting differential clock input 1
Non-inverting clock/data input 1
Input clock select. See Table 3 for function. Input Pulldown
Input clock select. See Table 3 for function. Input Pulldown
Output Enable Control. See Table 4 for function.
The Exposed Pad (EP) on the QFN−32 package bottom is
thermally connected to the die for improved heat transfer out
of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is electrically connected to the die,
and must be electrically connected to GND.
1. All VDD, VDDO
n
and GND pins must be externally connected to a power supply to guarantee proper operation. Bypass each V
DD
and VDDO
n
with 0.01
mF
CAP to GND.
Table 2. PIN CHARACTERISTICS
Symbol
C
IN
R
C
PD
Input Capacitance
Input Pulldown Resistor; Input Pulldown Resistor
Power Dissipation Capacitance (per output)
VDDO = 3.3 V
VDDO = 2.5 V
VDDO = 1.8 V
VDDO = 1.5 V
Output Impedance
VDDO = 3.3 V
VDDO = 2.5 V
VDDO = 1.8 V
VDDO = 1.5 V
Parameter
Min
Typ
4
50
Max
Unit
pF
kW
pF
R
OUT
W
20
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NB3F8L3010C
FUNCTION TABLES
Table 3. CLOCK ENABLE (SELx) FUNCTION TABLE
SEL[1:0] Input
00
01
10
11
Selected Input Clock
CLK0/CLK0
CLK1/CLK1
Crystal Osc Input
Crystal Osc Input
Table 5. DIFF IN/OUT TABLE (Diff or S.E.)
Input Condition
CLK0/1; CLK0/1 = OPEN
CLK0/1; CLK0/1 = GND
CLK0/1 = HIGH; CLK0/1 = LOW
CLK0/1 = LOW; CLK0/1 = HIGH
Output
Logic LOW
Undefined
Logic HIGH
Logic LOW
Table 4. CLOCK OUTPUT ENABLE (OE) FUNCTION
TABLE
OE Input
0
1
Q[9:0] Output
High Impedance
Outputs Enabled
Table 6. CRYSTAL CHARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Power
10
Min
Typ
Fundamental
50
50
7
100
MHz
W
pF
mW
Max
Unit
Table 7. ATTRIBUTES
Characteristic
ESD Protection
Moisture Sensitivity (Note 2)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
QFN32
Oxygen Index: 28 to 34
Value
>2 kV
200 V
Level 3
UL 94 V−0 @ 0.125 in
474 Devices
Table 8. MAXIMUM RATINGS
(Note 3)
Symbol
V
DD
,
VDDO
n
V
I
Positive Power Supply
Input Voltage
XTAL_IN
Diff, SELx, OE Inputs
Output Voltage
Operating Temperature Range, Industrial
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
0 lfpm
500 lfpm
(Note 3)
Parameter
Condition
GND = 0 V
Rating
4.6
Unit
V
V
0
v
V
I
v
V
DD
–0.5
v
V
I
v
V
DD
+ 0.5
– 0.5
v
V
O
v
VDDO
n
+ 0.5
−40 to +85
−65 to +150
31
27
12
V
O
T
A
T
stg
θ
JA
θ
JC
V
_C
_C
_C/W
_C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB3F8L3010C
Table 9. POWER SUPPLY DC CHARACTERISTICS
V
DD
= 3.3 V
±
5% (3.135 V to 3.465 V) or V
DD
= 2.5 V
±5%
(2.375 V to
2.625 V) and VDDO
n
= 3.3 V
±
5% (3.135 V to 3.465 V) or 2.5 V
±
5% (2.375 V to 2.625 V) or 1.8 V
±
0.2 V (1.6 V to 2.0 V) or 1.5 V
±
0.15 V (1.35 V to 1.65 V); T
A
= −40°C to 85°C
Symbol
IDD
Parameter
VDD Power Supply
Current
Test Conditions
OE = 0, no load
3.3 V
±
5%; VDDO
n
= 3.3 V
±
5% or 2.5 V
±
5% or
1.8 V
±
0.2 V or 1.5 V
±
0.15 V
2.5 V
±
5%; VDDO
n
= 2.5 V
±
5% or 1.8 V
±
0.2 V
or 1.5 V
±
0.15 V
OE = 0, no load
3.3 V
±
5%; VDDO
n
= 3.3 V
±
5% or 2.5 V
±
5% or
1.8 V
±
0.2 V or 1.5 V
±
0.15 V
2.5 V
±
5%; VDDO
n
= 2.5 V
±
5% or 1.8 V
±
0.2 V
or 1.5 V
±
0.15 V
Min
Typ
30
Max
50
Unit
mA
IDDO
VDDO Power Supply
Current
5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Table 10. DC CHARACTERISTICS
T
A
= −40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
LVCMOS / LVTTL Input High Voltage
(OE, SELx)
LVCMOS / LVTTL Input Low Voltage
(OE, SELx)
Input High Current
OE, SELx,
CLKx/CLKx
I
IL
Input Low Current
OE, SELx
CLKx
CLKx
V
OH
Output High Voltage (Note 4)
V
DD
= 3.465 V; V
IN
= 0.0 V
V
DD
= 3.465 V or 2.625 V V
IN
= 0.0 V
V
DD
= 3.465 V or 2.625 V V
IN
= 0.0 V
VDDO
n
= 3.3 V
±
5%
VDDO
n
= 2.5 V
±
5%
VDDO
n
= 1.8 V
±
0.2 V
VDDO
n
= 1.5 V
±
0.15 V
V
OL
Output Low Voltage (Note 4)
VDDO
n
= 3.3 V
±
5% or 2.5 V
±
5%
VDDO
n
= 1.8 V
±
0.2 V
VDDO
n
= 1.5 V
±
0.15 V
V
PP
V
IHCMR
Peak−to−Peak Input Voltage
V
IL
> −0.3 V
CLKx/CLKx
Input High Level Common Mode
Range
V
CM
= V
IH
; V
IL
>
−0.3 V CLKx/CLKx
V
DD
= 3.3 V
±5%
or V
DD
= 2.5 V
±
5%
V
DD
= 3.3 V
±5%
or V
DD
= 2.5 V
±
5%
0.15
0.5
−5
−5
−150
2.6
1.8
1.2
0.9
0.5
0.4
0.37
1.3
V
DD
− 0.85
V
V
V
V
V
DD
= V
IN
= 3.465 V
V
DD
= V
IN
= 3.465 V or 2.625 V
150
150
mA
Test Conditions
V
DD
= 3.3 V
±5%
V
DD
= 2.5 V
±
5%
V
DD
= 3.3 V
±5%
V
DD
= 2.5 V
±
5%
Min
2
1.7
−0.3
−0.3
Typ
Max
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
Unit
V
V
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
4. Outputs terminated with 50
W
to VDDO
n
/2. See Parameter Measurement Information..
Table 11. AC CHARACTERISTICS
V
DD
= 3.3 V
±
5% (3.135 V to 3.465 V) or V
DD
= 2.5 V
±5%
(2.375 V to 2.625 V) and
VDDO
n
= 3.3 V
±
5% (3.135 V to 3.465 V) or 2.5 V
±
5% (2.375 V to 2.625 V) or 1.8 V
±
0.2 V (1.6 V to 2.0 V) or 1.5 V
±
0.15 V (1.35 V
to 1.65 V); T
A
= −40°C to 85°C
Symbol
f
MAX
Parameter
Output Frequency
Using External
Crystal
Using External
Clock Source
(Note 5)
Test Conditions
Min
10
DC
Typ
Max
50
200
Unit
MHz
MHz
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