74AC191 Up/Down Counter with Preset and Ripple Clock
November 1988
Revised November 1999
74AC191
Up/Down Counter with Preset and Ripple Clock
General Description
The AC191 is a reversible modulo 16 binary counter. It fea-
tures synchronous counting and asynchronous presetting.
The preset feature allows the AC191 to be used in pro-
grammable dividers. The Count Enable input, the Terminal
Count output and the Ripple Clock output make possible a
variety of methods of implementing multistage counters. In
the counting modes, state changes are initiated by the ris-
ing edge of the clock.
Features
s
I
CC
reduced by 50%
s
High speed—133 MHz typical count frequency
s
Synchronous counting
s
Asynchronous parallel load
s
Cascadable
s
Outputs source/sink 24 mA
Ordering Code:
Order Number
74AC191SC
74AC191SJ
74AC191MTC
74AC191PC
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
CE
CP
P
0
–P
3
PL
U /D
Q
0
–Q
3
RC
TC
Description
Count Enable Input
Clock Pulse Input
Parallel Data Inputs
Asynchronous Parallel Load Input
Up/Down Count Control Input
Flip-Flop Outputs
Ripple Clock Output
Terminal Count Output
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009940
www.fairchildsemi.com
74AC191
RC Truth Table
Inputs
PL
H
H
H
L
CE
L
H
X
X
TC
(Note 1)
H
X
L
X
CP
Outputs
RC
X
X
X
H
H
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
=
Clock Pulse
Note 1:
TC is generated internally
Functional Description
The AC191 is a synchronous up/down counter. The AC191
is organized as a 4-bit binary counter. It contains four edge-
triggered flip-flops with internal gating and steering logic to
provide individual preset, count-up and count-down opera-
tions.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desired number.
When the Parallel Load (PL) input is LOW, information
present on the Parallel Load inputs (P
0
–P
3
) is loaded into
the counter and appears on the Q outputs. This operation
overrides the counting functions, as indicated in the Mode
Select Table.
A HIGH signal on the CE input inhibits counting. When CE
is LOW, internal state changes are initiated synchronously
by the LOW-to-HIGH transition of the clock input. The
direction of counting is determined by the U/D input signal,
as indicated in the Mode Select Table. CE and U/D can be
changed with the clock in either state, provided only that
the recommended setup and hold times are observed.
Two types of outputs are provided as overflow/underflow
indicators. The terminal count (TC) output is normally
LOW. It goes HIGH when the circuits reach zero in the
count down mode or 15 in the count up mode. The TC out-
put will then remain HIGH until a state change occurs,
whether by counting or presetting or until U/D is changed.
The TC output should not be used as a clock signal
because it is subject to decoding spikes.
The TC signal is also used internally to enable the Ripple
Clock (RC) output. The RC output is normally HIGH. When
CE is LOW and TC is HIGH, RC output will go LOW when
the clock next goes LOW and will stay LOW until the clock
goes HIGH again. This feature simplifies the design of mul-
tistage counters, as indicated in Figure 1 and Figure 2. In
Figure 1, each RC output is used as the clock input for the
next higher stage. This configuration is particularly advan-
tageous when the clock source has a limited drive capabil-
ity, since it drives only the first stage. To prevent counting in
all stages it is only necessary to inhibit the first stage, since
a HIGH signal on CE inhibits the RC output pulse, as indi-
cated in the RC Truth Table. A disadvantage of this config-
uration, in some applications, is the timing skew between
state changes in the first and last stages. This represents
the cumulative delay of the clock as it ripples through the
preceding stages.
A method of causing state changes to occur simulta-
neously in all stages is shown in Figure 2. All clock inputs
are driven in parallel and the RC outputs propagate the
carry/borrow signals in ripple fashion. In this configuration
the LOW state duration of the clock must be long enough to
allow the negative-going edge of the carry/borrow signal to
www.fairchildsemi.com
2
ripple through to the last stage before the clock goes HIGH.
There is no such restriction on the HIGH state duration of
the clock, since the RC output of any device goes HIGH
shortly after its CP input goes HIGH.
The configuration shown in Figure 3 avoids ripple delays
and their associated restrictions. The CE input for a given
stage is formed by combining the TC signals from all the
preceding stages. Note that in order to inhibit counting an
enable signal must be included in each carry gate. The
simple inhibit scheme of Figure 1 and Figure 2 doesn't
apply, because the TC output of a given stage is not
affected by its own CE.
Mode Select Table
Inputs
PL
H
H
L
H
CE
L
L
X
H
U/D
L
H
X
X
Mode
X
X
CP
Count Up
Count Down
Preset (Asyn.)
No Change (Hold)
State Diagram
74AC191
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
PDIP
140°C
±50
mA
−65°C
to
+150°C
±50
mA
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−0.5V
to
+7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (∆V/∆t)
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.3V 4.5V, 5.5V
125 mV/ns
2.0V to 6.0V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
Note 2:
Absolute maximum ratings are those values beyond which dam-
age to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its
power supply, temperature, output/input loading variables. Fairchild does
not recommend operation of FACT circuits outside databook specifica-
tions.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
(Note 5)
I
OLD
I
OHD
I
CC
(Note 5)
Maximum Input
Leakage Current
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
0.002
0.001
0.001
T
A
= +25°C
Typ
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
V
V
IN
=
V
IL
or V
IH
I
OL
=
12 mA
I
OL
=
24 mA
I
OL
=
24 mA (Note 3)
5.5
5.5
5.5
5.5
4.0
±0.1
±1.0
75
−75
40.0
µA
mA
mA
µA
V
I
=
V
CC
, GND
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
V
I
OUT
=
50
µA
V
V
IN
=
V
IL
or V
IH
I
OH
−12
mA
I
OH
= −24
mA
I
OH
.=
−24
mA (Note 3)
V
I
OUT
= −50 µA
V
V
OUT
=
0.1V
or V
CC
−
0.1V
V
V
OUT
=
0.1V
or V
CC
−
0.1V
Units
Conditions
Note 3:
All outputs loaded; thresholds on input associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
www.fairchildsemi.com
4
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
