Data Sheet, Rev. 1
December 2005
™
FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Features
1394a-2000 OHCI link and PHY core function in a sin-
gle device:
—
100-pin TQFP package (also available in a lead-free
package; see ordering information on page 85.)
— Single-chip link and PHY enable smaller, simpler,
more efficient motherboard and add-in card designs
— Enables lower system costs
— Leverages proven 1394a-2000 PHY core design
— Demonstrated compatibility with current
Microsoft
Windows
®
drivers and common applications
—
Demonstrated interoperability with existing, as well
as older, 1394 consumer electronics and peripherals
products
— Feature-rich implementation for high performance in
common applications
— Supports low-power system designs (CMOS imple-
mentation, power management features)
OHCI:
— Complies with the
1394 OHCI 1.1 Specification
— OHCI 1.0 backwards compatible—configurable via
EEPROM to operate in either OHCI 1.0 or OHCI 1.1
mode
— Complies with
Microsoft Windows
logo program
system and device requirements
— Listed on
Windows
hardware compatibility list
http://www.microsoft.com/hcl/results.asp
— Compatible with
Microsoft Windows
and
MacOS
®
operating systems
— 4 Kbyte isochronous transmit FIFO
— 2 Kbyte asynchronous transmit FIFO
— 4 Kbyte isochronous receive FIFO
— 2 Kbyte asynchronous receive FIFO
— Dedicated asynchronous and isochronous
descriptor-based DMA engines
— Eight isochronous transmit contexts
— Eight isochronous receive contexts
— Prefetches isochronous transmit data
— Supports posted write transactions
— Supports parallel processing of incoming physical
read and write requests
— Supports notification (via interrupt) of a failed
register access
— Information normally in the EEPROM can be pro-
grammed into the system BIOS.
1394a-2000 PHY core:
— Compliant with
IEEE
®
1394a-2000,
Standard for a
High Performance Serial Bus
(Supplement)
— Provides two fully compliant cable ports, each
supporting 400 Mbits/s, 200 Mbits/s, and
100 Mbits/s traffic
— Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders
— While unpowered and connected to the bus, will not
drive TPBIAS on a connected port even if receiving
incoming bias voltage on that port
— Does not require external filter capacitor for PLL
— Supports link-on as a part of the internal
PHY core-link interface
— 25 MHz crystal oscillator and internal PLL provide a
50 MHz
internal
link-layer controller clock as well
as
transmit/receive data at 100 Mbits/s, 200 Mbits/s,
and 400 Mbits/s.
— Interoperable across 1394 cable with 1394 physical
layers (PHY core) using 5 V supplies
— Provides node power-class information signaling for
system power management
— Supports ack-accelerated arbitration and fly-by
concatenation
— Supports arbitrated short bus reset to improve
utilization of the bus
— Fully supports suspend/resume
— Supports connection debounce
— Supports multispeed packet concatenation
— Supports PHY pinging and remote PHY access
packets
— Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V
Link:
— Cycle master and isochronous resource manager
capable
— Supports 1394a-2000 acceleration features
PCI:
— Revision 2.2 compliant
— 33 MHz/32-bit operation
— Programmable burst size thresholds for PCI data
transfer
— Supports optimized memory read line, memory read
multiple, and memory write invalidate burst
commands
— Supports
PCI Bus Power Management Interface
Specification
v.1.1.
Note:
This device does not support D3cold wakeup,
CLKRUN protocol,
mini PCI
®
applications, and
CardBus applications. Use the FW322 06 120-pin
TQFP device if one or more of these features are
needed.
FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Data Sheet, Rev. 1
December 2005
Table of Contents
Contents
Page
Features ................................................................................................................................................................... 1
Other Features....................................................................................................................................................6
FW322 Functional Overview .................................................................................................................................... 6
FW322 Functional Description ................................................................................................................................. 7
PCI Core .............................................................................................................................................................7
OHCI Data Transfer ............................................................................................................................................8
OHCI Isochronous Data Transfer .......................................................................................................................8
Isochronous Register Access .............................................................................................................................9
OHCI Asynchronous Data Transfer ....................................................................................................................9
Asynchronous Register Access ..........................................................................................................................9
Link Core ..........................................................................................................................................................11
PHY Core..........................................................................................................................................................13
Pin Information .......................................................................................................................................................15
Internal Registers ................................................................................................................................................... 21
PCI Configuration Registers .............................................................................................................................21
Vendor ID Register ...........................................................................................................................................22
Device ID Register ............................................................................................................................................22
PCI Command Register ....................................................................................................................................23
PCI Status Register ..........................................................................................................................................24
Class Code and Revision ID Registers.............................................................................................................25
Latency Timer and Cache Line Size Register ..................................................................................................25
Header Type and BIST Register.......................................................................................................................26
OHCI Base Address Register ...........................................................................................................................26
PCI Subsystem Identification Register .............................................................................................................27
PCI Power Management Capabilities Pointer Register ....................................................................................27
Interrupt Line and Pin Register .........................................................................................................................28
MIN_GNT and MAX_LAT Register ...................................................................................................................28
PCI OHCI Control Register ...............................................................................................................................29
Capability ID and Next Item Pointer Register ...................................................................................................29
Power Management Capabilities Register........................................................................................................30
Power Management Control and Status Register ............................................................................................31
Power Management CSR PCI-to-PCI Bridge Support Extensions ...................................................................32
Power Management Data .................................................................................................................................32
OHCI Registers.................................................................................................................................................33
OHCI Version Register .....................................................................................................................................36
GUID ROM Register .........................................................................................................................................37
Asynchronous Transmit Retries Register .........................................................................................................37
CSR Data Register ...........................................................................................................................................38
CSR Compare Register ....................................................................................................................................38
CSR Control Register .......................................................................................................................................38
Configuration ROM Header Register ................................................................................................................39
Bus Identification Register ................................................................................................................................40
Bus Options Register ........................................................................................................................................40
GUID High Register ..........................................................................................................................................41
GUID Low Register ...........................................................................................................................................41
Configuration ROM Mapping Register ..............................................................................................................42
Posted Write Address Low Register .................................................................................................................43
Posted Write Address High Register ................................................................................................................43
Vendor ID Register ...........................................................................................................................................43
Host Controller Control Register .......................................................................................................................44
SelfID Buffer Pointer Register...........................................................................................................................46
2
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Table of Contents
(continued)
Contents
Page
SelfID Count Register .......................................................................................................................................46
Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register .........................................47
Isochronous Receive Multiple Channel Mask Low (IRMultiChanMaskLo) Register .........................................47
Interrupt Event (IntEvent) Register ...................................................................................................................48
Interrupt Mask (IntMask) Register.....................................................................................................................50
Isochronous Transmit Interrupt Event (isoXmitIntMask) Register.....................................................................52
Isochronous Transmit Interrupt Mask (isoXmitIntMask) Register .....................................................................53
Isochronous Receive Interrupt Event (isoRecvIntEvent) Register ....................................................................54
Isochronous Receive Interrupt Mask (isoRecvIntMask) Register .....................................................................55
Fairness Control Register .................................................................................................................................55
Link Control Register ........................................................................................................................................56
Node Identification Register..............................................................................................................................57
PHY Core Layer Control Register.....................................................................................................................58
Isochronous Cycle Timer Register....................................................................................................................58
Asynchronous Request Filter High Register .....................................................................................................59
Asynchronous Request Filter Low Register......................................................................................................59
Physical Request Filter High Register ..............................................................................................................60
Physical Request Filter Low Register ...............................................................................................................60
Asynchronous Context Control Register...........................................................................................................61
Asynchronous Context Command Pointer Register .........................................................................................62
Isochronous Transmit Context Control (IT DMA ContextControl) Register ......................................................63
Isochronous Transmit Context Command Pointer Register..............................................................................64
Isochronous Receive Context Control (IR DMA ContextControl) Register .......................................................65
Isochronous Receive Context Command Pointer Register...............................................................................66
Isochronous Receive Context Match (IR DMA ContextMatch) Register...........................................................67
FW322 Vendor-Specific Registers....................................................................................................................68
Isochronous DMA Control.................................................................................................................................68
Asynchronous DMA Control..............................................................................................................................69
Link Options ......................................................................................................................................................70
Internal Register Configuration ...............................................................................................................................71
PHY Core Register Map ...................................................................................................................................71
PHY Core Register Fields.................................................................................................................................72
Crystal Selection Considerations ............................................................................................................................77
Load Capacitance .............................................................................................................................................77
Adjustment to Crystal Loading ..........................................................................................................................77
Crystal/Board Layout ........................................................................................................................................77
Serial EEPROM Interface .......................................................................................................................................78
ac Characteristics of Serial EEPROM Interface Signals ........................................................................................78
Solder Reflow and Handling ...................................................................................................................................81
Absolute Maximum Voltage/Temperature Ratings .................................................................................................81
Electrical Characteristics ........................................................................................................................................82
Timing Characteristics ............................................................................................................................................84
Outline Diagrams ....................................................................................................................................................85
100-Pin TQFP ...................................................................................................................................................85
Ordering Information ...............................................................................................................................................85
Agere Systems Inc.
3
FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Data Sheet, Rev. 1
December 2005
Table of Contents
(continued)
Figure
Page
Figure 1. FW322 Conceptual Block Diagram ...........................................................................................................6
Figure 2. PCI Core Block Diagram ...........................................................................................................................7
Figure 3. OHCI Core Block Diagram ........................................................................................................................8
Figure 4. Link Core Block Diagram ......................................................................................................................... 11
Figure 5. The PHY Core Block Diagram ................................................................................................................. 12
Figure 6. Pin Assignments for the FW322 06 T100 ................................................................................................ 15
Figure 7. Crystal Circuitry ....................................................................................................................................... 77
Figure 8. Bus Timing .............................................................................................................................................. 79
Figure 9. Write Cycle Timing .................................................................................................................................. 79
Figure 10. Data Validity .......................................................................................................................................... 79
Figure 11. Start and Stop Definition ....................................................................................................................... 80
Figure 12. Output Acknowledge ............................................................................................................................. 80
Table
Page
Table 1. Pin Descriptions ....................................................................................................................................... 16
Table 2. Bit-Field Access Tag Description ............................................................................................................. 21
Table 3. PCI Configuration Register Map ............................................................................................................. 21
Table 4. PCI Command Register Description ........................................................................................................ 23
Table 5. PCI Status Register ................................................................................................................................. 24
Table 6. Class Code and Revision ID Register Description .................................................................................. 25
Table 7. Latency Timer and Class Cache Line Size Register Description ........................................................... 25
Table 8. Header Type and BIST Register Description .......................................................................................... 26
Table 9. OHCI Base Address Register Description ............................................................................................... 26
Table 10. PCI Subsystem Identification Register Description ............................................................................... 27
Table 11. Interrupt Line and Pin Register Description ........................................................................................... 28
Table 12. MIN_GNT and MAX_LAT Register Description ..................................................................................... 28
Table 13. PCI OHCI Control Register Description ................................................................................................. 29
Table 14. Capability ID and Next Item Pointer Register Description ..................................................................... 29
Table 15. Power Management Capabilities Register Description ......................................................................... 30
Table 16. Power Management Control and Status Register Description .............................................................. 31
Table 17. Power Management Data Register Description .................................................................................... 32
Table 18. OHCI Register Map ............................................................................................................................... 33
Table 19. OHCI Version Register Description ....................................................................................................... 36
Table 20. GUID ROM Register Description ........................................................................................................... 37
Table 21. Asynchronous Transmit Retries Register Description ........................................................................... 37
Table 22. CSR Data Register Description ............................................................................................................. 38
Table 23. CSR Compare Register Description ...................................................................................................... 38
Table 24. CSR Control Register Description ........................................................................................................ 38
Table 25. Configuration ROM Header Register Description ................................................................................. 39
Table 26. Bus Identification Register Description .................................................................................................. 40
Table 27. Bus Options Register Description .......................................................................................................... 40
Table 28. GUID High Register Description ............................................................................................................ 41
Table 29. GUID Low Register Description ............................................................................................................. 41
Table 30. Configuration ROM Mapping Register Description ................................................................................ 42
Table 31. Posted Write Address Low Register Description ................................................................................... 43
Table 32. Posted Write Address High Register Description .................................................................................. 43
Table 33. Vendor ID Register Description ............................................................................................................. 43
Table 34. Host Controller Control Register Description ......................................................................................... 44
Table 35. SelfID Buffer Pointer Register Description ............................................................................................ 46
4
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Table of Contents
(continued)
Table
Page
Table 36. SelfID Count Register Description ......................................................................................................... 46
Table 37. Isochronous Receive Channel Mask High Register Description ........................................................... 47
Table 38. Isochronous Receive Channel Mask Low Register Description ............................................................ 47
Table 39. Interrupt Event Register Description ...................................................................................................... 48
Table 40. Interrupt Mask Register Description ...................................................................................................... 50
Table 41. Isochronous Transmit Interrupt Event Register Description .................................................................. 52
Table 42. Isochronous Transmit Interrupt Event Description ................................................................................ 53
Table 43. Isochronous Receive Interrupt Event Description ................................................................................. 54
Table 44. Fairness Control Register Description ................................................................................................... 55
Table 45. Link Control Register Description ......................................................................................................... 56
Table 46. Node Identification Register Description ............................................................................................... 57
Table 47. PHY Core Layer Control Register Description ...................................................................................... 58
Table 48. Isochronous Cycle Timer Register Description ..................................................................................... 58
Table 49. Asynchronous Request Filter High Register Description ....................................................................... 59
Table 50. Asynchronous Request Filter Low Register Description ....................................................................... 59
Table 51. Physical Request Filter High Register Description ................................................................................ 60
Table 52. Physical Request Filter Low Register Description ................................................................................. 60
Table 53. Asynchronous Context Control Register Description ........................................................................... 61
Table 54. Asynchronous Context Command Pointer Register Description ........................................................... 62
Table 55. Isochronous Transmit Context Control Register Description ................................................................ 63
Table 56. Isochronous Transmit Context Command Pointer Register Description ............................................... 64
Table 57. Isochronous Receive Context Control Register Description .................................................................. 65
Table 58. Isochronous Receive Context Command Pointer Register Description ................................................ 66
Table 59. Isochronous Receive Context Match Register Description ................................................................... 67
Table 60. FW322 Vendor-Specific Registers Description ..................................................................................... 68
Table 61. Isochronous DMA Control Registers Description .................................................................................. 68
Table 62. Asynchronous DMA Control Registers Description ............................................................................... 69
Table 63. Link Options Register Description ......................................................................................................... 70
Table 64. PHY Core Register Map ........................................................................................................................ 71
Table 65. PHY Core Register Fields ..................................................................................................................... 72
Table 66. PHY Core Register Page 0: Port Status Page ...................................................................................... 74
Table 67. PHY Core Register Port Status Page Fields ........................................................................................ 75
Table 68. PHY Core Register Page 1: Vendor Identification Page ....................................................................... 76
Table 69. PHY Core Register Vendor Identification Page Fields .......................................................................... 76
Table 70. ac Characteristics of Serial EEPROM Interface Signals ....................................................................... 78
Table 71. Absolute Maximum Ratings ................................................................................................................... 81
Table 72. Analog Characteristics ........................................................................................................................... 82
Table 73. Driver Characteristics ............................................................................................................................ 83
Table 74. Device Characteristics ........................................................................................................................... 83
Table 75. Switching Characteristics ...................................................................................................................... 84
Table 76. Clock Characteristics ............................................................................................................................. 84
Agere Systems Inc.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
