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FW323061394: 产品描述PCI PHY/Link Open Host Controller Interface; 文件大小497KB，共92页; 制造商Agere System(LSI Logic)

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PCI PHY/Link Open Host Controller Interface

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Data Sheet, Rev. 1

December 2005

™

FW323 06 1394a

PCI PHY/Link Open Host Controller Interface

Features

128

-pin TQFP lead-free package

1394a-2000 OHCI link and PHY core function in a single

device:

— Single-chip link and PHY enable smaller, simpler,

more efficient motherboard and add-in card designs

— Enables lower system costs

— Leverages proven 1394a-2000 PHY core design

— Demonstrated compatibility with current

Microsoft

Windows

drivers and common applications

— Demonstrated interoperability with existing, as well as

older, 1394 consumer electronics and peripherals

products

— Feature-rich implementation for high performance in

common applications

— Supports low-power system designs (CMOS imple-

mentation, power management features)

— Provides LPS, LKON, and CNA outputs to support

legacy power management implementations

OHCI:

— Complies with the 1394

OHCI 1.1 Specification

— OHCI 1.0 backwards compatible—configurable via

EEPROM to operate in either OHCI 1.0 or OHCI 1.1

mode

— Complies with

Microsoft Windows

logo program

system and device requirements

— Listed on

Windows

hardware compatibility list

http://www.microsoft.com/hcl/results.asp

— Compatible with

Microsoft Windows

and

MacOS

operating systems

— 4 Kbyte isochronous transmit FIFO

— 2 Kbyte asynchronous transmit FIFO

— 4 Kbyte isochronous receive FIFO

— 2 Kbyte asynchronous receive FIFO

— Dedicated asynchronous and isochronous descriptor-

based DMA engines

— Eight isochronous transmit contexts

— Eight isochronous receive contexts

— Prefetches isochronous transmit data

— Supports posted write transactions

— Supports parallel processing of incoming physical

read and write requests

— Supports notification (via interrupt) of a failed register

access

— May be used without an EEPROM when the system

BIOS is programmed with the EEPROM contents.

1394a-2000 PHY core:

— Compliant with

IEEE

1394a-2000,

Standard for a

High Performance Serial Bus

(Supplement)

— Three fully compliant cable ports, each supporting

400 Mbits/s, 200 Mbits/s, and 100 Mbits/s traffic

— Supports extended BIAS_HANDSHAKE time for

enhanced interoperability with camcorders

— While unpowered and connected to the bus, will not

drive TPBIAS on a connected port even if receiving

incoming bias voltage on that port

— Does not require external filter capacitor for PLL

— Supports link-on as a part of the internal

PHY core-link interface

— 25 MHz crystal oscillator and internal PLL provide a

50 MHz

internal

link-layer controller clock as well as

transmit/receive data at 100 Mbits/s, 200 Mbits/s, and

400 Mbits/s

— Interoperable across 1394 cable with 1394 physical

layers (PHY core) using 5 V supplies

— Provides node power-class information signaling for

system power management

— Supports ack-accelerated arbitration and fly-by

concatenation

— Supports arbitrated short bus reset to improve

utilization of the bus

— Fully supports suspend/resume

— Supports connection debounce

— Supports multispeed packet concatenation

— Supports PHY pinging and remote PHY access

packets

— Reports cable power fail interrupt when voltage at

CPS pin falls below 7.5 V

Link:

— Cycle master and isochronous resource manager

capable

— Supports 1394a-2000 acceleration features

PCI:

— Revision 2.2 compliant

— 33 MHz/32-bit operation

— Programmable burst size thresholds for PCI data

transfer

— Supports optimized memory read line, memory read

multiple, and memory write invalidate burst

commands

— Supports

PCI Bus Power Management Interface

Specification

v.1.1, including D3cold wakeups

— Supports CLKRUN# protocol per PCI Mobile Design

Guide

— Supports

Mini PCI Specification

v1.0, including Mini

PCI power requirements

— Global byte swap function

— CardBus support per PC Card Standard Release 8.0,

including 128 bytes of on-chip tuple memory.

FW323 06 1394a

PCI PHY/Link Open Host Controller Interface

Data Sheet, Rev. 1

December 2005

Table of Contents

Contents

Page

Features .................................................................................................................................................................. 1

Other Features .................................................................................................................................................. 6

FW323 Functional Overview ................................................................................................................................... 6

FW323 Functional Description ................................................................................................................................ 6

PCI Core ........................................................................................................................................................... 7

OHCI Data Transfer .......................................................................................................................................... 8

OHCI Isochronous Data Transfer ..................................................................................................................... 8

Isochronous Register Access ........................................................................................................................... 9

OHCI Asynchronous Data Transfer .................................................................................................................. 9

Asynchronous Register Access ........................................................................................................................ 9

Link Core ......................................................................................................................................................... 11

PHY Core ........................................................................................................................................................ 13

Pin Information ...................................................................................................................................................... 15

Internal Registers .................................................................................................................................................. 22

PCI Configuration Registers ........................................................................................................................... 22

Vendor ID Register ......................................................................................................................................... 24

Device ID Register .......................................................................................................................................... 24

PCI Command Register .................................................................................................................................. 25

PCI Status Register ........................................................................................................................................ 26

Class Code and Revision ID Registers ........................................................................................................... 27

Latency Timer and Cache Line Size Register ................................................................................................. 28

Header Type and BIST Register ..................................................................................................................... 28

OHCI Base Address Register ......................................................................................................................... 29

CardBus Base Address Register .................................................................................................................... 30

CIS Pointer ...................................................................................................................................................... 30

PCI Subsystem Identification Register ............................................................................................................ 31

PCI Power Management Capabilities Pointer Register ................................................................................... 31

Interrupt Line and Pin Register ....................................................................................................................... 32

MIN_GNT and MAX_LAT Register ................................................................................................................. 32

PCI OHCI Control Register ............................................................................................................................. 33

Capability ID and Next Item Pointer Register ................................................................................................. 33

Power Management Capabilities Register ...................................................................................................... 34

Power Management Control and Status Register ........................................................................................... 35

Power Management CSR PCI-to-PCI Bridge Support Extensions ................................................................. 36

Power Management Data ............................................................................................................................... 36

CardBus Function Registers (CardBusN = 0) ................................................................................................. 36

OHCI Registers ............................................................................................................................................... 37

OHCI Version Register ................................................................................................................................... 40

GUID ROM Register ....................................................................................................................................... 41

Asynchronous Transmit Retries Register ........................................................................................................ 41

CSR Data Register ......................................................................................................................................... 42

CSR Compare Register .................................................................................................................................. 42

CSR Control Register ..................................................................................................................................... 42

Configuration ROM Header Register .............................................................................................................. 43

Bus Identification Register .............................................................................................................................. 44

Bus Options Register ...................................................................................................................................... 44

GUID High Register ........................................................................................................................................ 45

GUID Low Register ......................................................................................................................................... 45

Configuration ROM Mapping Register ............................................................................................................ 46

Posted Write Address Low Register ............................................................................................................... 47

Posted Write Address High Register .............................................................................................................. 47

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW323 06 1394a

PCI PHY/Link Open Host Controller Interface

Table of Contents

(continued)

Contents

Page

Vendor ID Register ..........................................................................................................................................

Host Controller Control Register .....................................................................................................................

SelfID Buffer Pointer Register .........................................................................................................................

SelfID Count Register .....................................................................................................................................

Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register .......................................

Isochronous Receive Multiple Channel Mask Low (IRMultiChanMaskLo) Register .......................................

Interrupt Event (IntEvent) Register ..................................................................................................................

Interrupt Mask (IntMask) Register ...................................................................................................................

Isochronous Transmit Interrupt Event (isoXmitIntMask) Register ...................................................................

Isochronous Transmit Interrupt Mask (isoXmitIntMask) Register ...................................................................

Isochronous Receive Interrupt Event (isoRecvIntEvent) Register ..................................................................

Isochronous Receive Interrupt Mask (isoRecvIntMask) Register ...................................................................

Fairness Control Register ...............................................................................................................................

Link Control Register .......................................................................................................................................

Node Identification Register ............................................................................................................................

PHY Core Layer Control Register ...................................................................................................................

Isochronous Cycle Timer Register ..................................................................................................................

Asynchronous Request Filter High Register ...................................................................................................

Asynchronous Request Filter Low Register ....................................................................................................

Physical Request Filter High Register .............................................................................................................

Physical Request Filter Low Register .............................................................................................................

Asynchronous Context Control Register .........................................................................................................

Asynchronous Context Command Pointer Register ........................................................................................

Isochronous Transmit Context Control (IT DMA ContextControl) Register .....................................................

Isochronous Transmit Context Command Pointer Register ............................................................................

Isochronous Receive Context Control (IR DMA ContextControl) Register .....................................................

Isochronous Receive Context Command Pointer Register .............................................................................

Isochronous Receive Context Match (IR DMA ContextMatch) Register .........................................................

FW323 Vendor-Specific Registers ..................................................................................................................

Isochronous DMA Control ...............................................................................................................................

Asynchronous DMA Control ............................................................................................................................

Link Options ....................................................................................................................................................

Internal Register Configuration ..............................................................................................................................

PHY Core Register Map ..................................................................................................................................

PHY Core Register Fields ...............................................................................................................................

Crystal Selection Considerations ...........................................................................................................................

Load Capacitance ...........................................................................................................................................

Adjustment to Crystal Loading ........................................................................................................................

Crystal/Board Layout .......................................................................................................................................

Serial EEPROM Interface ......................................................................................................................................

ac Characteristics of Serial EEPROM Interface Signals ........................................................................................

NAND Tree Testing ................................................................................................................................................

Solder Reflow and Handling ..................................................................................................................................

Absolute Maximum Voltage/Temperature Ratings .................................................................................................

Electrical Characteristics .......................................................................................................................................

Timing Characteristics ...........................................................................................................................................

Outline Diagrams ...................................................................................................................................................

128-Pin TQFP .................................................................................................................................................

Ordering Information ..............................................................................................................................................

Agere Systems Inc.

FW323 06 1394a

PCI PHY/Link Open Host Controller Interface

Data Sheet, Rev. 1

December 2005

Table of Contents

(continued)

Figure

Page

Figure 1. FW323 Conceptual Block Diagram ........................................................................................................... 6

Figure 2. PCI Core Block Diagram ........................................................................................................................... 7

Figure 3. OHCI Core Block Diagram ........................................................................................................................ 8

Figure 4. Link Core Block Diagram ......................................................................................................................... 11

Figure 5. The PHY Core Block Diagram ................................................................................................................. 12

Figure 6. Pin Assignments for the FW323 06 ......................................................................................................... 15

Figure 7. Crystal Circuitry ....................................................................................................................................... 81

Figure 8. Bus Timing .............................................................................................................................................. 83

Figure 9. Write Cycle Timing .................................................................................................................................. 83

Figure 10. Data Validity .......................................................................................................................................... 83

Figure 11. Start and Stop Definition ....................................................................................................................... 84

Figure 12. Output Acknowledge ............................................................................................................................. 84

Figure 13. Nand Tree Logic Structure .................................................................................................................... 86

Table

Page

Table 1. Pin Descriptions ....................................................................................................................................... 16

Table 2. Bit-Field Access Tag Description ............................................................................................................. 22

Table 3a. PCI Configuration Register Map, CardBusN = 1 ................................................................................... 22

Table 3b. PCI Configuration Register Map, CardBusN = 0 ................................................................................... 23

Table 4. PCI Command Register Description ........................................................................................................ 25

Table 5. PCI Status Register ................................................................................................................................. 26

Table 6. Class Code and Revision ID Register Description .................................................................................. 27

Table 7. Latency Timer and Class Cache Line Size Register Description ........................................................... 28

Table 8. Header Type and BIST Register Description .......................................................................................... 28

Table 9. OHCI Base Address Register Description ............................................................................................... 29

Table 10. CardBus Base Address Register Description ........................................................................................ 30

Table 11. PCI Subsystem Identification Register Description ............................................................................... 31

Table 12. Interrupt Line and Pin Register Description ........................................................................................... 32

Table 13. MIN_GNT and MAX_LAT Register Description ..................................................................................... 32

Table 14. PCI OHCI Control Register Description ................................................................................................. 33

Table 15. Capability ID and Next Item Pointer Register Description ..................................................................... 33

Table 16. Power Management Capabilities Register Description ......................................................................... 34

Table 17. Power Management Control and Status Register Description .............................................................. 35

Table 18. Power Management Data Register Description .................................................................................... 36

Table 19. OHCI Register Map ............................................................................................................................... 37

Table 20. OHCI Version Register Description ....................................................................................................... 40

Table 21. GUID ROM Register Description ........................................................................................................... 41

Table 22. Asynchronous Transmit Retries Register Description ........................................................................... 41

Table 23. CSR Data Register Description ............................................................................................................. 42

Table 24. CSR Compare Register Description ...................................................................................................... 42

Table 25. CSR Control Register Description ........................................................................................................ 42

Table 26. Configuration ROM Header Register Description ................................................................................. 43

Table 27. Bus Identification Register Description.................................................................................................. 44

Table 28. Bus Options Register Description .......................................................................................................... 44

Table 29. GUID High Register Description ............................................................................................................ 45

Table 30. GUID Low Register Description ............................................................................................................. 45

Table 31. Configuration ROM Mapping Register Description ................................................................................ 46

Table 32. Posted Write Address Low Register Description ................................................................................... 47

Table 33. Posted Write Address High Register Description .................................................................................. 47

Table 34. Vendor ID Register Description ............................................................................................................. 47

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW323 06 1394a

PCI PHY/Link Open Host Controller Interface

Table of Contents

(continued)

Table

Page

Table 35. Host Controller Control Register Description ......................................................................................... 48

Table 36. SelfID Buffer Pointer Register Description ............................................................................................ 50

Table 37. SelfID Count Register Description ......................................................................................................... 50

Table 38. Isochronous Receive Channel Mask High Register Description ........................................................... 51

Table 39. Isochronous Receive Channel Mask Low Register Description ............................................................ 51

Table 40. Interrupt Event Register Description ...................................................................................................... 52

Table 41. Interrupt Mask Register Description ...................................................................................................... 54

Table 42. Isochronous Transmit Interrupt Event Register Description .................................................................. 56

Table 43. Isochronous Transmit Interrupt Event Description ................................................................................ 57

Table 44. Isochronous Receive Interrupt Event Description ................................................................................. 58

Table 45. Fairness Control Register Description ................................................................................................... 59

Table 46. Link Control Register Description ......................................................................................................... 60

Table 47. Node Identification Register Description ............................................................................................... 61

Table 48. PHY Core Layer Control Register Description ...................................................................................... 62

Table 49. Isochronous Cycle Timer Register Description ..................................................................................... 62

Table 50. Asynchronous Request Filter High Register Description ....................................................................... 63

Table 51. Asynchronous Request Filter Low Register Description ....................................................................... 63

Table 52. Physical Request Filter High Register Description ................................................................................ 64

Table 53. Physical Request Filter Low Register Description ................................................................................. 64

Table 54. Asynchronous Context Control Register Description ........................................................................... 65

Table 55. Asynchronous Context Command Pointer Register Description ........................................................... 66

Table 56. Isochronous Transmit Context Control Register Description ................................................................ 67

Table 57. Isochronous Transmit Context Command Pointer Register Description ............................................... 68

Table 58. Isochronous Receive Context Control Register Description .................................................................. 69

Table 59. Isochronous Receive Context Command Pointer Register Description ................................................ 70

Table 60. Isochronous Receive Context Match Register Description ................................................................... 71

Table 61. FW323 Vendor-Specific Registers Description ..................................................................................... 72

Table 62. Isochronous DMA Control Registers Description .................................................................................. 72

Table 63. Asynchronous DMA Control Registers Description ............................................................................... 73

Table 64. Link Options Register Description ......................................................................................................... 74

Table 65. PHY Core Register Map ........................................................................................................................ 75

Table 66. PHY Core Register Fields ..................................................................................................................... 76

Table 67. PHY Core Register Page 0: Port Status Page ...................................................................................... 78

Table 68. PHY Core Register Port Status Page Fields ........................................................................................ 79

Table 69. PHY Core Register Page 1: Vendor Identification Page ....................................................................... 80

Table 70. PHY Core Register Vendor Identification Page Fields .......................................................................... 80

Table 71. ac Characteristics of Serial EEPROM Interface Signals ....................................................................... 82

Table 72. NAND Tree Testing ............................................................................................................................... 85

Table 73. Absolute Maximum Ratings ................................................................................................................... 87

Table 74. Analog Characteristics ........................................................................................................................... 88

Table 75. Driver Characteristics ............................................................................................................................ 89

Table 76. Device Characteristics ........................................................................................................................... 89

Table 77. Switching Characteristics ...................................................................................................................... 90

Table 78. Clock Characteristics ............................................................................................................................. 90

Agere Systems Inc.

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FW323061394

FW323061394概述

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