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FW322061394: 产品描述PCI PHY/Link Open Host Controller Interface; 文件大小467KB，共92页; 制造商Agere System(LSI Logic)

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PCI PHY/Link Open Host Controller Interface

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Data Sheet, Rev. 1

December 2005

™

FW322 06 1394a

PCI PHY/Link Open Host Controller Interface

Features

1394a-2000 OHCI link and PHY core function in a

single device:

— Single-chip link and PHY enable smaller, simpler,

more efficient motherboard and add-in card

designs

— Enables lower system costs

— Leverages proven 1394a-2000 PHY core design

— Demonstrated compatibility with current

Microsoft

Windows

drivers and common appli-

cations

— Demonstrated interoperability with existing, as

well as older, 1394 consumer electronics and

peripherals products

— Feature-rich implementation for high perfor-

mance in common applications

— Supports low-power system designs (CMOS

implementation, power management features)

— Provides LPS, LKON, and CNA outputs to sup-

port legacy power management implementations

OHCI:

— Complies with the 1394

OHCI 1.1 Specification

— OHCI 1.0 backwards compatible—configurable

via EEPROM to operate in either OHCI 1.0 or

OHCI 1.1 mode

— Complies with

Microsoft Windows

logo program

system and device requirements

— Listed on

Windows

hardware compatibility list

http://www.microsoft.com/windows/catalog/

— Compatible with

Microsoft Windows

and

MacOS

operating systems

— 4 Kbyte isochronous transmit FIFO

— 2 Kbyte asynchronous transmit FIFO

— 4 Kbyte isochronous receive FIFO

— 2 Kbyte asynchronous receive FIFO

— Dedicated asynchronous and isochronous

descriptor-based DMA engines

— Eight isochronous transmit contexts

— Eight isochronous receive contexts

— Prefetches isochronous transmit data

— Supports posted write transactions

— Supports parallel processing of incoming phys-

ical read and write requests

— Supports notification (via interrupt) of a failed

— May be used without an EEPROM when the sys-

tem BIOS is programmed with the EEPROM con-

tents.

1394a-2000 PHY core:

— Compliant with

IEEE

1394a-2000,

Standard for

a High Performance Serial Bus

(Supplement)

— Provides two fully compliant cable ports, each

supporting 400 Mbits/s, 200 Mbits/s, and

100 Mbits/s traffic

— Supports extended BIAS_HANDSHAKE time for

enhanced interoperability with camcorders

— While unpowered and connected to the bus, will

not drive TPBIAS on a connected port even if

receiving incoming bias voltage on that port

— Does not require external filter capacitor for PLL

— Supports link-on as a part of the internal

PHY core-link interface

— 25 MHz crystal oscillator and internal PLL

provide a 50 MHz internal link-layer controller

clock as well as transmit/receive data at

100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.

— Interoperable across 1394 cable with 1394 phys-

ical layers (PHY core) using 5 V supplies

— Provides node power-class information signaling

for system power management

— Supports ack-accelerated arbitration and fly-by

concatenation

— Supports arbitrated short bus reset to improve

utilization of the bus

— Fully supports suspend/resume

— Supports connection debounce

— Supports multispeed packet concatenation

— Supports PHY pinging and remote PHY access

packets

— Reports cable power fail interrupt when voltage

at CPS pin falls below 7.5 V

— Provides separate cable bias and driver termina-

tion voltage supply for each port

Link:

— Cycle master and isochronous resource

manager capable

— Supports 1394a-2000 acceleration features

FW322 06 1394a

PCI PHY/Link Open Host Controller Interface

Data Sheet, Rev. 1

December 2005

Table of Contents

Contents

Page

Features ................................................................................................................................................................... 1

Other Features....................................................................................................................................................6

FW322 Functional Overview .................................................................................................................................... 6

FW322 Functional Description ................................................................................................................................. 6

PCI Core .............................................................................................................................................................7

OHCI Data Transfer............................................................................................................................................8

OHCI Isochronous Data Transfer .......................................................................................................................8

Isochronous Register Access .............................................................................................................................9

OHCI Asynchronous Data Transfer ....................................................................................................................9

Asynchronous Register Access ..........................................................................................................................9

Link Core ..........................................................................................................................................................11

PHY Core..........................................................................................................................................................13

Pin Information ....................................................................................................................................................... 15

Internal Registers ................................................................................................................................................... 22

PCI Configuration Registers .............................................................................................................................22

Vendor ID Register ...........................................................................................................................................24

Device ID Register............................................................................................................................................24

PCI Command Register....................................................................................................................................25

PCI Status Register ..........................................................................................................................................26

Class Code and Revision ID Registers.............................................................................................................27

Latency Timer and Cache Line Size Register ..................................................................................................28

Header Type and BIST Register.......................................................................................................................28

OHCI Base Address Register ...........................................................................................................................29

CardBus Base Address Register ......................................................................................................................30

CIS Pointer .......................................................................................................................................................30

PCI Subsystem Identification Register .............................................................................................................31

PCI Power Management Capabilities Pointer Register ....................................................................................31

Interrupt Line and Pin Register .........................................................................................................................32

MIN_GNT and MAX_LAT Register...................................................................................................................32

PCI OHCI Control Register...............................................................................................................................33

Capability ID and Next Item Pointer Register ...................................................................................................33

Power Management Capabilities Register........................................................................................................34

Power Management Control and Status Register ............................................................................................35

Power Management CSR PCI-to-PCI Bridge Support Extensions ...................................................................36

Power Management Data .................................................................................................................................36

CardBus Function Registers (CardBusN = 0)...................................................................................................36

OHCI Registers.................................................................................................................................................37

OHCI Version Register .....................................................................................................................................40

GUID ROM Register .........................................................................................................................................41

Asynchronous Transmit Retries Register .........................................................................................................41

CSR Data Register ...........................................................................................................................................42

CSR Compare Register ....................................................................................................................................42

CSR Control Register .......................................................................................................................................42

Configuration ROM Header Register................................................................................................................43

Bus Identification Register ................................................................................................................................44

Bus Options Register........................................................................................................................................44

GUID High Register ..........................................................................................................................................45

GUID Low Register...........................................................................................................................................45

Configuration ROM Mapping Register..............................................................................................................46

Posted Write Address Low Register .................................................................................................................47

Posted Write Address High Register ................................................................................................................47

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 1394a

PCI PHY/Link Open Host Controller Interface

Table of Contents

(continued)

Contents

Page

Vendor ID Register ...........................................................................................................................................47

Host Controller Control Register.......................................................................................................................48

SelfID Buffer Pointer Register...........................................................................................................................50

SelfID Count Register .......................................................................................................................................50

Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register.........................................51

Isochronous Receive Multiple Channel Mask Low (IRMultiChanMaskLo) Register .........................................51

Interrupt Event (IntEvent) Register ...................................................................................................................52

Interrupt Mask (IntMask) Register ....................................................................................................................54

Isochronous Transmit Interrupt Event (isoXmitIntMask) Register ....................................................................56

Isochronous Transmit Interrupt Mask (isoXmitIntMask) Register .....................................................................57

Isochronous Receive Interrupt Event (isoRecvIntEvent) Register....................................................................58

Isochronous Receive Interrupt Mask (isoRecvIntMask) Register .....................................................................59

Fairness Control Register .................................................................................................................................59

Link Control Register ........................................................................................................................................60

Node Identification Register..............................................................................................................................61

PHY Core Layer Control Register.....................................................................................................................62

Isochronous Cycle Timer Register....................................................................................................................62

Asynchronous Request Filter High Register.....................................................................................................63

Asynchronous Request Filter Low Register......................................................................................................63

Physical Request Filter High Register ..............................................................................................................64

Physical Request Filter Low Register ...............................................................................................................64

Asynchronous Context Control Register...........................................................................................................65

Asynchronous Context Command Pointer Register .........................................................................................66

Isochronous Transmit Context Control (IT DMA ContextControl) Register ......................................................67

Isochronous Transmit Context Command Pointer Register .............................................................................68

Isochronous Receive Context Control (IR DMA ContextControl) Register.......................................................69

Isochronous Receive Context Command Pointer Register ..............................................................................70

Isochronous Receive Context Match (IR DMA ContextMatch) Register ..........................................................71

FW322 Vendor-Specific Registers....................................................................................................................72

Isochronous DMA Control.................................................................................................................................72

Asynchronous DMA Control .............................................................................................................................73

Link Options......................................................................................................................................................74

Internal Register Configuration ...............................................................................................................................75

PHY Core Register Map ...................................................................................................................................75

PHY Core Register Fields.................................................................................................................................76

Crystal Selection Considerations............................................................................................................................ 81

Load Capacitance.............................................................................................................................................81

Adjustment to Crystal Loading..........................................................................................................................81

Crystal/Board Layout ........................................................................................................................................81

Serial EEPROM Interface....................................................................................................................................... 82

ac Characteristics of Serial EEPROM Interface Signals ........................................................................................ 82

NAND Tree Testing ................................................................................................................................................ 85

Solder Reflow and Handling ................................................................................................................................... 87

Absolute Maximum Voltage/Temperature Ratings ................................................................................................. 87

Electrical Characteristics ........................................................................................................................................ 88

Timing Characteristics ............................................................................................................................................ 90

Outline Diagrams.................................................................................................................................................... 91

120-Pin TQFP...................................................................................................................................................91

Ordering Information............................................................................................................................................... 91

Agere Systems Inc.

FW322 06 1394a

PCI PHY/Link Open Host Controller Interface

Data Sheet, Rev. 1

December 2005

Table of Contents

(continued)

Figure

Page

Figure 1. . FW322 Conceptual Block Diagram ........................................................................................................ 6

Figure 2. . PCI Core Block Diagram ........................................................................................................................ 7

Figure 3. . OHCI Core Block Diagram ..................................................................................................................... 8

Figure 4. . Link Core Block Diagram ...................................................................................................................... 11

Figure 5. . The PHY Core Block Diagram .............................................................................................................. 12

Figure 6. . Pin Assignments for the FW322 06 ...................................................................................................... 15

Figure 7. . Crystal Circuitry .................................................................................................................................... 81

Figure 8. . Bus Timing ........................................................................................................................................... 83

Figure 9. . Write Cycle Timing ............................................................................................................................... 83

Figure 10. . Data Validity ....................................................................................................................................... 83

Figure 11. . Start and Stop Definition .................................................................................................................... 84

Figure 12. . Output Acknowledge .......................................................................................................................... 84

Figure 13. Nand Tree Logic Structure ................................................................................................................... 86

Table

Page

Table 1. Pin Descriptions ....................................................................................................................................... 16

Table 2. Bit-Field Access Tag Description ............................................................................................................. 22

Table 3. PCI Configuration Register Map, CardBusN = 1 ..................................................................................... 22

Table 4. PCI Configuration Register Map, CardBusN = 0 ..................................................................................... 23

Table 5. PCI Command Register Description ........................................................................................................ 25

Table 6. PCI Status Register ................................................................................................................................. 26

Table 7. Class Code and Revision ID Register Description .................................................................................. 27

Table 8. Latency Timer and Class Cache Line Size Register Description ........................................................... 28

Table 9. Header Type and BIST Register Description .......................................................................................... 28

Table 10. OHCI Base Address Register Description ............................................................................................. 29

Table 11. CardBus Base Address Register Description ........................................................................................ 30

Table 12. PCI Subsystem Identification Register Description ............................................................................... 31

Table 13. Interrupt Line and Pin Register Description ........................................................................................... 32

Table 14. MIN_GNT and MAX_LAT Register Description ..................................................................................... 32

Table 15. PCI OHCI Control Register Description ................................................................................................. 33

Table 16. Capability ID and Next Item Pointer Register Description ..................................................................... 33

Table 17. Power Management Capabilities Register Description ......................................................................... 34

Table 18. Power Management Control and Status Register Description .............................................................. 35

Table 19 Power Management Data Register Description ..................................................................................... 36

Table 20. OHCI Register Map ............................................................................................................................... 37

Table 21. OHCI Version Register Description ....................................................................................................... 40

Table 22. GUID ROM Register Description ........................................................................................................... 41

Table 23. Asynchronous Transmit Retries Register Description ........................................................................... 41

Table 24. CSR Data Register Description ............................................................................................................. 42

Table 25. CSR Compare Register Description ...................................................................................................... 42

Table 26. CSR Control Register Description ........................................................................................................ 42

Table 27. Configuration ROM Header Register Description ................................................................................. 43

Table 28. Bus Identification Register Description .................................................................................................. 44

Table 29. Bus Options Register Description .......................................................................................................... 44

Table 30. GUID High Register Description ............................................................................................................ 45

Table 31. GUID Low Register Description ............................................................................................................. 45

Table 32. Configuration ROM Mapping Register Description ................................................................................ 46

Table 33. Posted Write Address Low Register Description ................................................................................... 47

Table 34. Posted Write Address High Register Description .................................................................................. 47

Table 35. Vendor ID Register Description ............................................................................................................. 47

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 1394a

PCI PHY/Link Open Host Controller Interface

Table of Contents

(continued)

Table

Page

Table 36. Host Controller Control Register Description ......................................................................................... 48

Table 37. SelfID Buffer Pointer Register Description ............................................................................................ 50

Table 38. SelfID Count Register Description ......................................................................................................... 50

Table 39. Isochronous Receive Channel Mask High Register Description ........................................................... 51

Table 40. Isochronous Receive Channel Mask Low Register Description ............................................................ 51

Table 41. Interrupt Event Register Description ...................................................................................................... 52

Table 42. Interrupt Mask Register Description ...................................................................................................... 54

Table 43. Isochronous Transmit Interrupt Event Register Description .................................................................. 56

Table 44. Isochronous Transmit Interrupt Event Description ................................................................................ 57

Table 45. Isochronous Receive Interrupt Event Description ................................................................................. 58

Table 46. Fairness Control Register Description ................................................................................................... 59

Table 47. Link Control Register Description ......................................................................................................... 60

Table 48. Node Identification Register Description ............................................................................................... 61

Table 49. PHY Core Layer Control Register Description ...................................................................................... 62

Table 50. Isochronous Cycle Timer Register Description ..................................................................................... 62

Table 51. Asynchronous Request Filter High Register Description ....................................................................... 63

Table 52. Asynchronous Request Filter Low Register Description ....................................................................... 63

Table 53. Physical Request Filter High Register Description ................................................................................ 64

Table 54. Physical Request Filter Low Register Description ................................................................................. 64

Table 55. Asynchronous Context Control Register Description ........................................................................... 65

Table 56. Asynchronous Context Command Pointer Register Description ........................................................... 66

Table 57. Isochronous Transmit Context Control Register Description ................................................................ 67

Table 58. Isochronous Transmit Context Command Pointer Register Description ............................................... 68

Table 59. Isochronous Receive Context Control Register Description .................................................................. 69

Table 60. Isochronous Receive Context Command Pointer Register Description ................................................ 70

Table 61. Isochronous Receive Context Match Register Description ................................................................... 71

Table 62. FW322 Vendor-Specific Registers Description ..................................................................................... 72

Table 63. Isochronous DMA Control Registers Description .................................................................................. 72

Table 64. Asynchronous DMA Control Registers Description ............................................................................... 73

Table 65. Link Options Register Description ......................................................................................................... 74

Table 66. PHY Core Register Map ........................................................................................................................ 75

Table 67. PHY Core Register Fields ..................................................................................................................... 76

Table 68. PHY Core Register Page 0: Port Status Page ...................................................................................... 78

Table 69. PHY Core Register Port Status Page Fields ........................................................................................ 79

Table 70. PHY Core Register Page 1: Vendor Identification Page ....................................................................... 80

Table 71. PHY Core Register Vendor Identification Page Fields .......................................................................... 80

Table 72. ac Characteristics of Serial EEPROM Interface Signals ....................................................................... 82

Table 73. NAND Tree Testing ............................................................................................................................... 85

Table 74. Absolute Maximum Ratings ................................................................................................................... 87

Table 75. Analog Characteristics ........................................................................................................................... 88

Table 76. Driver Characteristics ............................................................................................................................ 89

Table 77. Device Characteristics ........................................................................................................................... 89

Table 78. Switching Characteristics ...................................................................................................................... 90

Table 79. Clock Characteristics ............................................................................................................................. 90

Agere Systems Inc.

FW322061394相似产品对比

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描述	PCI PHY/Link Open Host Controller Interface	PCI PHY/Link Open Host Controller Interface

FW322061394

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