74ABT544
Octal latched transceiver with dual enable; 3-state
Rev. 6 — 3 November 2011
Product data sheet
1. General description
The 74ABT544 high performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT544 octal latched transceiver contains two sets of D-type latches for temporary
storage of data flowing in either direction. Separate latch enable (LEAB, LEBA) and output
enable (OEAB, OEBA) inputs are provided for each register to permit independent control
of data transfer in either direction. The outputs are guaranteed to sink 64 mA.
2. Features and benefits
Combines 74ABT640 and 74ABT373 type functions in one device
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Live insertion and extraction permitted
Output capability: +64 mA to
32
mA
Power-up 3-state
Power-up reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74ABT544D
74ABT544DB
74ABT544PW
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
Name
SO24
SSOP24
TSSOP24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT137-1
SOT340-1
SOT355-1
Type number
NXP Semiconductors
74ABT544
Octal latched transceiver with dual enable; 3-state
4. Functional diagram
2
23
1
13
11
14
1EN3 (BA)
G1
1C5
2EN4 (AB)
G2
2C6
22
21
20
19
18
17
16
15
001aae901
3
4
5
6
7
8
9
10
3
11
23
14
1
A0 A1 A2 A3 A4 A5 A6 A7
EAB
EBA
LEAB
LEBA
B0 B1 B2 B3 B4 B5 B6 B7
22 21 20 19 18 17 16 15
001aae900
3
6D
5D
2
4
5
OEAB
OEBA
13
2
6
7
8
9
10
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
OEBA
2
13
OEAB
EBA
LEBA
23
1
11
14
EAB
LEAB
DETAIL A
D
LE
A0
3
Q
D
LE
Q
22
B0
4
A1
5
A2
6
A3
7
A4
8
A5
9
A6
10
A7
DETAIL A
×
7
21
20
19
18
17
16
15
001aac758
B1
B2
B3
B4
B5
B6
B7
Fig 3.
Logic diagram
74ABT544
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
2 of 16
NXP Semiconductors
74ABT544
Octal latched transceiver with dual enable; 3-state
5. Pinning information
5.1 Pinning
74ABT544
LEBA
OEBA
A0
A1
A2
A3
A4
A5
A6
1
2
3
4
5
6
7
8
9
24 V
CC
23 EBA
22 B0
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 LEAB
13 OEAB
001aac755
A7 10
EAB 11
GND 12
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Symbol
LEBA
OEBA
A0 to A7
EAB
GND
OEAB
LEAB
B0 to B7
EBA
V
CC
Pin description
Pin
1
2
3, 4, 5, 6, 7, 8, 9, 10
11
12
13
14
22, 21, 20, 19, 18, 17, 16, 15
23
24
Description
B-to-A latch enable input (active LOW)
B-to-A output enable input (active LOW)
data input or output
A-to-B enable input (active LOW)
ground (0 V)
A-to-B output enable input (active LOW)
A-to-B latch enable input (active LOW)
data input or output
B-to-A enable input (active LOW)
positive supply voltage
74ABT544
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
3 of 16
NXP Semiconductors
74ABT544
Octal latched transceiver with dual enable; 3-state
6. Functional description
6.1 Function table
Table 3.
Input
OEXX
H
X
L
L
L
L
[1]
Function selection
[1]
Output
EXX
X
H
L
L
L
LEXX
X
X
L
L
H
An or Bn
X
X
h
l
h
l
H
L
X
Bn or An
Z
Z
Z
Z
L
H
L
H
NC
hold
transparent
latch + display
disabled + latch
disabled
Status
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
= LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
6.2 Description
The 74ABT544 contains two sets of eight D-type latches, with separate control pins for
each set.
Using data flow from A-to-B as an example, when the A-to-B enable (EAB) input, the
A-to-B latch enable (LEAB) input and the A-to-B output enable (OEAB) input are all LOW,
the A-to-B path is transparent.
A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches
where it is stored and the B outputs no longer change with the A inputs. With EAB and
OEAB both LOW, the 3-state B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B-to-A is similar, but using the EBA, LEBA, and OEBA inputs.
74ABT544
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
4 of 16
NXP Semiconductors
74ABT544
Octal latched transceiver with dual enable; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
j
T
stg
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
junction temperature
storage temperature
Conditions
[1]
Min
0.5
1.2
0.5
18
50
-
[2]
Max
+7.0
+7.0
+5.5
-
-
128
150
+150
Unit
V
V
V
mA
mA
mA
C
C
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
[1]
-
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
t/V
T
amb
Recommended operating conditions
Parameter
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
input transition rise and fall rate
ambient temperature
in free air
Conditions
Min
4.5
0
2.0
-
32
-
0
40
Typ
-
-
-
-
-
-
-
-
Max
5.5
V
CC
-
0.8
-
64
10
+85
Unit
V
V
V
V
mA
mA
ns/V
C
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol
V
IK
V
OH
Parameter
Conditions
Min
input clamping voltage V
CC
= 4.5 V; I
IK
=
18
mA
HIGH-level output
voltage
V
I
= V
IL
or V
IH
V
CC
= 4.5 V; I
OH
=
3
mA
V
CC
= 5.0 V; I
OH
=
3
mA
V
CC
= 4.5 V; I
OH
=
32
mA
V
OL
LOW-level output
voltage
V
CC
= 4.5 V; I
OL
= 64 mA;
V
I
= V
IL
or V
IH
2.5
3.0
2.0
-
3.2
3.7
2.3
0.42
-
-
-
0.55
2.5
3.0
2.0
-
-
-
-
0.55
V
V
V
V
1.2
25
C
Typ
0.9
Max
-
40 C
to +85
C
Unit
Min
1.2
Max
-
V
74ABT544
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
5 of 16
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